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Scientists have devised a chip design to ensure microprocessors haven't been surreptitiously equipped with malicious backdoors that could be used to siphon sensitive information or receive instructions from adversaries.

The on-chip engines at the heart of these "tamper evident microprocessors" are the computer equivalent of cellophane shrink wrap or aluminum seals that flag food or drug packages that have been opened by someone other than the consumer. They're designed to monitor operations flowing through a CPU for signs its microcode has been altered by malicious insiders during the design cycle.

"The root of trust in all software systems rests on microprocessors because all software is executed by a microprocessor," the scientists, from Columbia University's computer science department, wrote in their paper describing the design. "If the microprocessor cannot be trusted, no security guarantees can be provided by the system."

At the heart of their proposal are two engines hardwired into a processor that continuously monitor chip communications for anomalies. One of the engines, dubbed TrustNet, sends an alert whenever a unit executes more or fewer instructions than is expected. A second, called DataWatch, watches chip data for signs the CPU has been maliciously modified.

The engines are built to detect a variety of potential threats such as emitter backdoors, which typically append instructions to a processor's normal batch of communications so that data is copied to "shadow addresses" that can later be accessed by the attackers. They're also built to flag corrupter backdoors that subtly alter microarchitectural operations.

The defenses are premised on the assumption that the backdoors would be installed by insiders working in a single sub-unit of a design team. While a well-funded nation state could afford to buy out an entire team, the more likely scenario is that adversaries would be much more limited, the researchers said. The insiders would add the hidden instructions during the RTL, or register transfer level, phase of design, which involves writing the microcode that controls a chip's functions.

The scientists demonstrated the design on a simplified OpenSPARC T2 processor from Sun Microsystems and got promising results. All emitter and control corrupter attacks were flagged in all cases, and no false positives occurred. They also said the added performance costs were negligible, with less than 3 KB of storage required per processor core.

The scientists are Adam Waksman and Simha Sethumadhavan. A PDF of their paper is here. ®

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