Toshiba, Western Digital put away lawyers long enough to play 96-layer 3D NAND game of Jenga

Tosh talks 4-level cell tech, too

By Chris Mellor

Posted in Storage, 28th June 2017 19:10 GMT

Just as we are getting used to 64‑layer 3D NAND chips, along come the warring flash joint-venture couple Toshiba and Western Digital. The pair say their JV has produced a 96‑layer prototype die, with Toshiba also introducing four-level cell tech.

A 96‑layer 3D NAND chip has 50 per cent more layers than a 64‑layer chip, and thus, nominally, 50 per cent more capacity. However, it’s not actually working like that yet. Toshiba says its latest chip, using its BiCS4 technology, has a capacity increase of approximately 40 per cent per unit chip size over the 64‑layer stacking process.

Its prototype 96‑layer 3bits/cell (TLC) die has 256Gbit capacity – half that of its shipping 64‑layer die.

This 96‑layer BiCS flash will be manufactured at Toshiba’s and WDC’s Yokkaichi Operations in Fab 5, the new Fab 2, and Fab 6, which will open in summer 2018.

Toshiba will build 512Gbit chips using 96 layers in the future, as well as adding a 4‑bits/cell (QLC) product, while WDC talks about a 1Tbit chip in the future.

Dr Siva Sivaram, EVP for memory technology at Western Digital, said: “BiCS4 will be available in 3-bits-per-cell and 4-bits-per-cell architectures ... Western Digital’s 3D NAND portfolio is designed to address the full range of end markets spanning consumer, mobile, computing and data center.”

Toshiba has announced the world’s first QLC die with 768Gbit capacity, using the current 64‑layer 3D technology. It says this QLC flash memory enables a 1.5TB device with a 16‑die stacked architecture in a single package; the industry’s largest capacity solid state device.

Toshiba and WDC say samples of their 96‑layer product are scheduled for release in the second half of 2017 and mass production is targeted for 2018. Applications include enterprise and consumer SSDs, smartphones, tablets and memory cards.

The two also believe their combined 64‑layer 3D NAND bit output from their joint venture will be higher than any other industry supplier in calendar 2017.

Samples of Toshiba’s QLC device began shipping in June to SSD and SSD controller vendors for evaluation and development purposes. They will be showcased at the 2017 Flash Memory Summit, taking place August 7‑10 in Santa Clara, California.

Amid all the above tech stuff, all is not well between Tosh and WDC. Today Toshiba is suing WDC in Tokyo for ¥120bn ($1bn, £830m), alleging unfair competition and that WDC has "interfered" with the bid process related to the sale of Toshiba’s Memory Corporation business.

Reg comment

QLC flash will have a low endurance rating – in the low hundreds of cycles, perhaps even lower – rendering it suitable only for archival use cases in enterprises, where reads heavily outnumber writes. The situation here is that there may be a large population of files, such as photo images or videos or podcasts, which are needed instantly when requested; the Facebook user checking photo albums is one such scenario.

This will have a cost, compared to slower off-line tape archives in vaults or tape libraries, but much faster access. Access will be faster than disk as well, and such flash-based archives should have lower power requirements and smaller space needs than disk-based archives, meaning lower cost.

Reliability, price and performance compared to disk and tape archives will be the key characteristics that will dictate whether QLC flash drive archives will succeed or fail. ®

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