Xilinx's high-end Versal FPGA is like a designer handbag. If you need to ask the price, you probably can't afford it
Premium chip is 7nm, 4 Arm CPU cores, up to 7.4 million logic cells, multi-Tbps networking and crypto
Xilinx will today announce an FPGA that is a little bananas: the Versal Premium, aimed at cloud builders and telcos.
It's the sort of component that if you need to ask how much it costs, it's probably not for you. Instead, you need to specify how many you need, and the price will be calculated from there.
It includes a boatload of fixed silicon for performing networking, signal processing, and encryption at high speed, CPU cores running application code, and a big block of reconfigurable circuitry that can be arranged to accelerate specific workloads in hardware.
The reprogrammable hardware can be designed using high-level languages, such as C/C++, or low-level SystemVerilog and the like. It can be reconfigured within tens of milliseconds, we're told, so you can imagine one of these in a cloud server or a telco's routing gear, loading in different blocks of customized hardware acceleration on demand, and processing packets, video transcoding, analytics, or AI stuff in real-time as information flows through.
This TSMC-fabricated 7nm chip has dual-core Arm Cortex-A72 and dual-core Arm Cortex-R5F CPUs for running application code to direct the FPGA's operation. It sports PCIe 5 interfaces with DMA, CCIX, and CXL support; a DDR4 controller for external memory; 5Tbps of on-board Ethernet interface throughput; 1.8Tbps of Interlaken networking; 1.6Tbps of line-rate encryption; 9Tbps of PAM4 transceiver bandwidth; DSP engines; and other bits and pieces. There's also up to 1Gb of tightly coupled on-die memory.
The reconfigurable hardware slab contains up to 7.4 million system logic cells, which is a lot, and 3.4 million look-up tables (LUTs). That's enough to simulate your own CPU core, though that's not really the intended use case.
Xilinx is pitching this at organizations that would like to use their own customized silicon in cloud and communications infrastructure, but don't really want to splash out $25m-plus to develop their own chips over three to four years. Instead, they can opt for an FPGA in the short-term that has a shedload of programmable gates for speeding up custom workloads, and a clump of built-in acceleration for encryption and networking.
The cryptography engines, for one, support AES-GCM-256 and 128, MACsec, and IPsec.
The Versal Premium silicon, part of the ACAP family, is due to ship as samples in the first half of next year. Documentation is available now, if you want to take a look, and tools to prototype and configure it are expected to land in the second half of 2020.
The Versal Prime, the Premium's more modest sibling, was unveiled in 2018 for a 2019 launch. ®