Who's been copying AMD's homework? Intel lifts the lid on its hip chip packaging to break up chips into chiplets
Interconnects, never sexy but very useful for Chipzilla's plans
With Moore's so-called Law pretty much dead for now, and the shrinking of transistors proving more difficult, the name of the game today is packing multiple dies into chip packages rather than cramming more and more smaller transistors into the same area of silicon.
Single dies packed with large numbers of cores and transistors are a magnificent pain in the ass to manufacture reliably. So, processors these days are heading toward being a collection of multiple smaller dies arranged in a single large package.
As such Intel sees its future in building custom chips out of these smaller "chiplets," and has given details on the interconnect technology it has developed to make it happen.
The tech, called Omni-Directional Interconnect (ODI), enables communication between multiple stacked chiplets in a single integrated circuit package; this should enable Chipzilla to quickly assemble products from a list of interchangeable parts.
Intel has also shared more details on how Foveros – its 3D stacking tech announced earlier this year – and Embedded Multi-die Interconnect Bridge (EMIB) will be used to create more capable silicon.
Chip packaging is the not-so-sexy, bread and butter kind of thing: everybody wants to know the core count and frequency of your CPUs, GPUs and FPGAs, but very few people are interested in technologies which define how the slab of silicon will be mounted on the motherboard and supplied with power.
Intel sees chips of the future as modular constructs, assembled for specific tasks out of readily available parts. To make this happen, it is essential to be able to stick more than one silicon die into the package.
“Our vision is to develop leadership technology to connect chips and chiplets in a package to match the functionality of a monolithic system-on-chip,” explained Babak Sabi, veep for Assembly and Test Technology Development at Intel, on Tuesday.
“A heterogeneous approach gives our chip architects unprecedented flexibility to mix and match IP blocks and process technologies with various memory and I/O elements in new device form factors.”
Using ODI, the top chip can communicate with other chiplets in the package horizontally; vertical communication is ensured thanks to through-silicon vias (TSVs) in the base die below.
According to Intel, ODI leverages vias that are much larger than traditional TSVs and thus offer lower resistance, allowing power delivery to the top die directly from the package substrate. They also enable higher bandwidth and lower latency.
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At the same time, this approach reduces the number of TSVs required in the base die, either freeing up more area for active transistors, or helping shrink die size.
Intel has also developed a new die-to-die interface called MDIO, intended as a replacement for the Advanced Interface Bus (AIB) standard currently used in Stratix FPGAs. MDIO promises better power efficiency and more than double the pin speed and bandwidth density offered by AIB.
And finally, Intel has merged its embedded multi-die interconnect bridge (EMIB) and Foveros technologies into something called co-EMIB. The former is already found on the Kaby Lake-G processors that integrate AMD’s GPU cores and HBM memory, while the latter takes the 3D stacking approach, beloved by memory manufacturers – when chips are soldered face-to-face - and applies it to CPU and FPGA design.
co-EMIB allows for the interconnection of two or more Foveros elements to deliver performance that’s close to a single, unbroken piece of silicon – at least according to Intel. ®
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