All nodes lead to Rome: Epyc leak spills deets on second-gen Zen 32-core AMD server chippery
But what is the significance of lower clock speeds?
Benchmarks of engineering samples of AMD's second-generation Zen-based server processor silicon, codenamed Rome, have once again found their way online.
Back in March, we saw stats detailing the performance of the chip designer's upcoming 64-core, 128-thread flagship second-gen Epyc part. The info was revealed to the world by an anonymous user of SiSoftware's Sandra – a popular UK-made PC analysis and diagnostics tool that's been going strong since 1997 and includes the option to share benchmark results publicly online. The entry was subsequently deleted – but not before everyone managed to take a screenshot.
Now, Sandra has outed the chip's 32-core, 64-thread sibling, spotted by Tom's Hardware on Saturday and identified as ZS1711E3VIVG5_24/17_N.
According to the database, the mid-range chip will offer base clock of 1.7GHz and 2.4GHz in turbo mode, with 16MB of Level 2 cache and 128MB of Level 3 cache.
What's immediately noticeable is a slight reduction in clock frequency from the first generation, 32-core Epyc 7601. This could be the result of practical challenges of moving manufacturing from 14nm to the 7nm process. If true, AMD is likely lowering the clock speeds while increasing the number of instructions executed per clock cycle.
Sandra awarded the chip a score of 1545.59Mpix/s for multimedia processing, rating the performance as "excellent". The system as a whole ranked as 631 globally out of millions of machines tested on the platform. Since this is an engineering sample, the numbers should be treated with caution – it is entirely possible that the production chips will be clocked higher.
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There's no info on TDP, but all of the chips based on Ryzen cores generally consume a bit less power and produce less heat than comparable parts from Intel. This is a far cry from the days of AMD's Bulldozer and Piledriver chips, which, anecdotally, doubled up as portable space heaters.
Both the 64-core and the 32-core chips leaked were recorded as running in Dell PowerEdge servers, with product numbers that haven't been announced anywhere else – R7515 and R6515. Dell was an early adopter of the first-generation Epycs, and it's a safe bet it will be one of the first to support the latest crop of silicon.
With Rome, AMD boosts its maximum core count on a single chip to 64, while Intel's latest generation Xeon SP Platinum 9200 Series maxes out at 56 cores – and is still made on the 14nm process.
Rome is expected to be officially launched during a keynote at Computex on 27 May and will begin shipping in the third quarter of the year – as per a roadmap revealed in April. ®