On the first day of Christmas, MIPS sent to me: An open-source-ish alternative to RISC-V

AI biz Wave Computing on Monday told the world it intends to open source the latest MIPS instruction set architecture (ISA) in the hope that fosters the development of more RISC-based custom chips.

The outfit acquired MIPS, the fabless CPU design firm that had been sold twice before since 2013, back in June with the intention of using its well-established processor tech for running AI code on IoT devices at the edge of the network.

Wave said under its MIPS Open Initiative, participants – who will be required to register – will have access to the 32-bit and 64-bit MIPS ISA at no charge, without any licensing or royalty fees. The key thing here is instruction set: the machine-code language your, for instance, C source compiles down to. It's how the chip interfaces with software. It's not how the insides of a processor works.

"The intention is to open source the ISA in same fashion as RISC-V is an open source architecture," said Art Swift, president of Wave Computing's MIPS IP Business, in a phone interview with The Register, referring to the freely available RISC-V ISA. "It's the latest commercial version that people used to pay millions of dollars for."

If enough customers were still doing so, it's unlikely anything would have changed. MIPS' open source conversion follows growing interest in the open source RISC-V ISA – very similar to MIPS, technically – as a way to develop custom system-on-chip hardware without the expense of an Arm license.

The RISC-V project began in 2010 and only a few years ago it was still viewed as experimental. With the recent arrival of RISC-V hardware in the market, backing from Western Digital, Nvidia, Google, and others, and a partnership between the RISC-V Foundation and the Linux Foundation, those involved with MIPS appear to have realized that remaining proprietary becomes difficult when there's a comparable open source alternative and opportunities to win back market share from x86 and Arm architectures look slim.

Wave Computing is banking on the fact that MIPS hardware is still widespread in the market, with more than eight billion MIPS chips shipped. Asked how he'd distinguish MIPS from RISC-V, Swift said, "The major difference is that MIPS has been proven and historically is one of the most famous RISC architectures." Indeed it is or was: it's powered tons of stuff from high-end SGI workstations in the late 1980s and 1990s to games consoles and spacecraft to network gear, and so on.

Swift said the goal is to complete the open source transition by the end of Q1 2019. Along the way, he said, Wave intends to announce partners and a governance structure for the open source project.

The program will include access to: the open source version of the 32-bit and 64-bit MIPS ISA, Release 6; MIPS SIMD Extensions; MIPS DSP Extensions; MIPS Multi-Threading; MIPS MCU; microMIPS Architecture; and MIPS Virtualization. It does not include any PU core designs at the moment – the blueprints needed to fabricate your own processor – but Swift said Wave Computing is considering the release of one or two.

The point really is to take the MIPS ISA and craft your own CPU core implementation from the specification, if you so desire. On the other hand, you could take a look at open-source implementations of RISC-V or ask Arm for a bargain-basement core.

Swift declined to specify the license under which MIPS will be offered. But he characterized it as a "simple, non-royalty bearing license," one that doesn't include a requirement to make core designs available to the community.

Given that and the registration requirement, the MIPS Open Initiative sounds more like source-available than open source.

Those wishing to use the MIPS logo and to enjoy the shelter of the MIPS patent portfolio will need to seek certification, for which there will be a yet-to-be-determined fee. "If you want to maintain patent coverage, you need to certify your implementation," said Swift. "If you don't, you're on your own." ®