Arms race: SiFive, Hex Five build code safe houses for RISC-V chips
Those developing custom CPUs can now tap a TrustZone-ish trusted execution environment
If you've been looking at SiFive's RISC-V-based chip technology and thinking, y'know what, it's missing an Arm TrustZone-style element to run sensitive code, well, here's some good news.
And if you're just into processor design and checking out alternatives to Arm CPU cores, then this may be some interesting news.
SiFive helps organizations turn semiconductor designs based on the open-source RISC-V instruction set architecture (ISA) into chips. On Monday, it announced it has integrated Hex Five Security's MultiZone Security trusted execution environment (TEE) into its Freedom SDK.
The technical confection gives companies creating RISC-V chips the tools to implement a security environment comparable to ARM's TrustZone, though perhaps without past flaws. It should help users of the SiFive toolchain bring security-enforcing silicon to market faster.
Hex Five's technology, as its name suggests, allows for the creation of multiple isolated zones in which sensitive code – such as secure boot procedures and cryptographic routines – can run without interference from other programs or operating systems executing at the same time. It works with a Configurator tool that combines the compiled code with a Hex Five nanokernel to run within the secured environment.
TEEs partition the processor in distinct zones and attempt to maintain separation between them to the extent that's possible. Related work is being done by MIT and UC Berkeley boffins to develop an open source secure enclave called Keystone, one component in a TEE.
In a phone interview with The Register, Don Barnetson, cofounder of Hex Five, explained that the TEE sits at the bare metal level and is used to secure the root of trust and authentication below the operating system. A secure enclave like Keystone, he said, would be used to secure a Linux app from other pieces of Linux.
He sees Keystone as complementary to MultiZone.
"RISC-V is an open source ISA," he said. "The ISA is the contract between the software and hardware. MultiZone allows you to secure that ISA for the first time. Security is often so complicated that people just don't bother. Our goal is to make it easier."
MultiZone is being made available through the SiFive Software Ecosystem program, by which participating vendors provide hardware-making customers with IP at little or not cost, to allow chip products to be brought to market before IP bills come due.
"History shows that the complexity associated with properly implementing security technologies often results in them not being used at all," said Cesare Garlati, co-founder of Hex-Five, in a statement. "Our mission is to enable mainstream adoption of security best practices by simplifying their deployment."
The RISC-V ISA, backed by the RISC-V Foundation and companies such Google, Nvidia, Western Digital, and Samsung, among others, offers an open, royalty-free set of instruction that companies can use in custom processors.
Chip designer Arm, which charges for its silicon blueprints, has had its feathers ruffled by RISC-V because it represents a potential competitor, once the project matures. The Softbank-owned company launched an anti-RISC-V website in late June, and then removed it after about two weeks after criticism from its own staff and the broader tech industry. ®
PS: As well as Hex Five's work, Inside Secure has a root-of-trust element implementation for RISC-V chips and processors using other ISAs, too.