EU plans for domestic exascale supercomputer chips: A RISC-y business

Consortium possibly looking to flex Arm muscle, too

EU parliament photo2 via Shutterstock

Analysis The European Union's consortium to develop European microprocessors for future supercomputers has taken a few more steps towards its goal of delivering a locally made exascale chip by 2025.

Just the chips, ma'am

The EPI is just the processor part of the EuroHPC Joint Undertaking. General manager and project co-ordinator Philippe Notton, an ATOS VP, in charge of EPI processor development, has made clear that it does not involve the intended exascale machine’s memory or interconnect or the actual building of the machine.

In June, a European Investment Bank (EIB) report - Financing the future of supercomputing - mentioned building a European exascale capability with mainly European hardware.

Just a month before, a presentation (PDF) by Barcelona Supercomputing Center (BSC) director Professor Mateo Valero, looking at the EPI and RISC-V, provided a timetable slide. His presentation showed four Specific Grant Agreement (SGA) phases. It envisaged two processor chip development efforts. First is a general HPC processor chip and system technology with Arm identified as candidate technology. Generation one of this will go into pre-exascale machines in 2021-2022. Gen two will go into an exascale system in 2023-2025.

The second stream appeared to be for an accelerator chip and system with RISC-V identified as the architecture. There would be two generations of this chipset along with a general purpose processor. BSC leads the accelerator chip and system development activities.

A third generation system-on-chip would combine the general CPU cores and acceleration cores, and be ready in 2024/2025 for use in an automotive CPU product. This chip is depicted in a blurry fashion, an indication it’s not a well defined idea.

There was a second key market on Valero’s slide, the automotive market, with the idea being to produce a CPU for use in autonomous vehicles. BMW was named as one of 23 partners involved in the EPI.

There are so far no other European carmakers named as being involved, not Fiat, Mercedes, Peugeot, Renault, nor the VW group.

EPI chip design

Notton has spoken about the general HPC chip effort. It is required to be a low power processor in terms of electricity usage (performance/watt). He talks about a single processor with two dimensions - general and accelerative - and having an ecosystem around this.

The EPI processor man then said the general processor’s architecture has not been fixed, with Arm being one of the candidates and negotiations being ongoing. A public product brief of specifications was anticipated to be ready for August.

ATOS is involved with Arm in the Arm-using Mont Blanc 2020 supercomputer, as is the Barcelona Supercomputing Center (BSC).


Mont Blanc supercomputer

OpenPower is another candidate architecture. However the use of Arm seems to be a foregone conclusion as Notton said: “Most of the IP that will be developed as part of Mont-Blanc 2020 will be reused and productized in EPI. In fact the IP that will be used in the European Processor Initiative will come from Mont-Blanc 2020, will also come from the external world, and some parts will be developed within EPI, like the accelerator technology.”

Desire for European technology

EPI's chip man has said that the exascale system cannot be fully European because Europe lacks indigenous technologies needed, such as CPUs and memory.

He told Primeur magazine: “That is why, as part of this consortium, we are going to start our own processor development which is based on RISC-V, and develop some IP and ecosystem around it. We do not start from zero, because there is some instruction set and elements which are ready. Unfortunately, it is not at HPC production level yet and it will take a couple of generations.”

The Euro exascale system will use off-the-shelf memory (HBM3) but European-developed memory controller, Network-On-Chip (NOC), interconnect and power management technology. Nothing has yet been said about storage and its software. The EPI aspect is restricted to the processors, low level software, like an SDK, and compilers.

The other hardware and system middleware is the responsibility of the EuroHPC program. Notton added: “The building of the complete machine with 10k - 50k processors, is also part of the EuroHPC programme.”

The EPI gen 1 chip timescales were described by Notton: “The timescale that we put in the project plan is that the first demo is in 2020. We expect the chip to be alive in the second part of 2020, and ready for production in 2021, which should be in line with the pre-exascale demonstrator.”


The biggest hole in the Euro HPC exascale system is the entire stack above the processors, and an exascale-ready ecosystem of suppliers and users. This stack’s development hinges on the processor/accelerator architecture, which hasn’t been identified yet. The timetable looks challenging.

The EU has seven years to get this development completed, and that would be three years after US exascale systems are scheduled, four years after Japan’s Post-K, and five years after China’s Tianhe-3. ®

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