Another dimension, new galaxy. Intergalactic planar-tary: Join us on our 3D NAND journey
Part two of our look into storage world's transition from 2D
Analysis Part one of my attempt to understand the transition from 2D to 3D NAND started out by trying to understand how 2D NAND is made, so that its development towards 3D NAND can be understood.
To recap just a little, a crucial aspect of 2D or planar NAND is that it is made up of bitline strings – individual cells connected in series and laid out in rows across a flash die, with word lines running at right angles to the bit lines but not touching them.
We'll use Toshiba's BiCS (Bit Cost Scalable) 3D NAND to illustrate what happens.
The first 3D NAND concept to grasp is that planar NAND cells are flipped vertically, so that previously horizontal cells become perpendicular ones.
Toshiba BiCS concept with upright pillars of NAND cells. The red lines are the bitlines. The green layers represent word line sheets with select gate sheets at the top and bottom
Secondly, in Toshiba's BiCS scheme the strings of cells are lengthened in the middle, to form a space there, and then formed into a U shape with the space at the bottom and the two sides standing upright.
This is a conceptual diagram; it's not how the stuff is made.
Let's use another diagram to relate this bit line string folding to Toshiba's BiCS concept above.
Toshiba BiCS diagram showing folded bitline strings
What happens to the word lines and bitlines?
In 2D NAND, the word lines are horizontal strips of polysilicon. In 3D NAND they are horizontal sheets of the stuff. How are the alternating layers made in a semiconductor process?
Jim Handy writes:
First a layer of CMOS logic is built on the chip to serve as the peripheral logic, and conductive paths are produced on the substrate to connect pairs of adjacent columns to form the U‑shaped cell [structure]. This logic is then insulated with a layer of silicon dioxide. A conductive polysilicon layer is deposited on top of this to form the first wordline and control gate, and a silicon dioxide layer is grown on top of the polysilicon to insulate it from the polysilicon layer that will be deposited above it.
This is repeated a number of times, with pairs of polysilicon and silicon dioxide layers laid one above another as sheets across the entire wafer. It's something like a layer cake with alternating layers of cake and frosting.
Then an array of circular holes must be cut – by etching – into this flash chemical component layer cake down to the substrate, and filled with alternating components to construct the flash cell structure.
Handy tells us, "The holes in 3D NAND only go through the layers that are only about 2.5-3µm or 1/15th-1/20th the height of a TSV. These holes are used to build the NAND strings."
We can visualise this with yet another diagram:
Step 2 is the etching of a hole. Step 3 is coating the inside of the hole with the dielectric oxide to form an insulating layer between the control gate and the floating gate.
Step 4 creates the floating gate(s) by depositing a Silicon Nitride charge trap lining onto the now narrower hole's walls. Oxide is used to line that in step 5 and so insulate it from the Polysilicon filling formed in step 6.
An unlabelled SanDisk image illustrates the end result:
My guess is that (working out from the center) the gray center is a SiO2 fill, the yellow is the polysilicon channel, the blue is the tunnel dielectric, the green is a charge trapping layer, the next blue is the gate dielectric, but I don't know what the pink layer would be. The control gates are the red horizontal layers, and the insulator between bits, a horizontal SiO2 layer, is not shown in order to add clarity.
The more layers there are, the more precise and accurate the hole etching has to be and the more difficult it is to get a uniform deposition layer on the inside of these etched holes. The aspect ratio needs to be controlled to an extraordinary degree.
Next the "up" bitline string so constructed needs to have its control gates separated from the equivalent "down" string's control gates. Long slits are cut into the length of the array between adjacent connected columns to accomplish this.
Shrinking 3D NAND's cell geometry is different from shrinking planar NAND cell size. Handy says: "Shrinking the cell size involves thinning the layers. The issue ... is that shrinking the diameter of a hole would worsen the aspect ratio. This is taboo."
We need to understand that there are different kinds of holes in 3D NAND chips.
Vias are holes that run partly through a silicon die.
Jim Handy tells us, "TSVs do go all the way through the die/wafer. On the other hand, the vertical connections that are made in nearly all chips are simply called 'vias.' These vias typically penetrate a single thickness of silicon dioxide, something like 10nm. Sometimes they will go through a number of these layers, maybe 5. Still, that's 1/1,000th the 50µm depth of a TSV."
Vias need to have their depth controlled precisely so that they stop at the right layer in the right material.
Micron and Intel and Samsung and SK Hynix have their own 3D NAND manufacturing processes that will differ from Toshiba's in detail. But we can use the understanding of the Toshiba process to get an insight into the fiendishly difficult and complex manufacturing process needed to make 3D NAND chips. ®