Gather round, kids, and let's try to understand the science of 3D NAND
Part 1: Start with the flat 2D planar stuff
Backgrounder The world of flash is moving to 3D NAND, chips with 36, 48, 72 or 64 layers of flash cells, and 96-layer chips being prototyped. How has it developed from 2D NAND?
To say 2D or planar NAND is a single layer of flash cells is true, as is saying that 3D NAND is layered, but 3D NAND is not actually manufactured from layers of 2D NAND stacked one on top of the other.
It's actually made from flipping the orientation of 2D NAND cells from horizontal to perpendicular and then having strings or pillars of flash cells, one above the other. This has consequences for how the die is constructed.
To understand these consequences we need to have a grasp on how 2D NAND is laid out.
2D planar NAND
A NAND cell consists of the cell itself, wordlines and bitlines. The cell is a transistor, a floating-gate MOSFET (Metal Oxide Semiconductor Field Effect Transistor), which stores an electrical charge. It is composed of a control gate above and separated from a floating gate by insulating material or dielectric, such as SiO2, which also separates the floating gate from an underlying substrate.
It signals binary 1 or 0 status by whether there are electrons in the floating gate component or not. When there are, no current flows through the transistor and the logic or binary value is 0.
When electrons are taken away from the floating gate, the transistor conducts electricity and that signals a binary 1. The cell is operated by pumping electrons into or taking electrons away from the floating gate.
Flash cell diagram
A wordline is a horizontal strip of polysilicon, a hyper-pure form of silicon, and it connects the to the transistor's (cell's) control gate.
A bitline is connected to a cell's drain. Different voltage combinations applied to the wordline and bitline define a read, erase or write (program) operation on the cell. The charge or absence thereof in the floating gate affects the threshold at which current will flow across the control+floating gate combination.
An erased NAND cell has a negative threshold voltage while a programed cell has a positive threshold voltage.
Reading a cell involves applying a current to the control gate and then seeing if current flows from the cell's source to its drain. If current flow is absent then the floating gate is charged with electrons (binary 0). A binary 1 is when current does flow from the source to the drain, with the floating gate not being charged.
To write or program a cell, a higher voltage is applied to the control gate, which causes electrons to move from the underlying substrate across the insulating layer into the floating gate (charging).
Erasing a cell involves applying a high voltage to the substrate so that electrons flow from the floating gate across the insulating layer into the substrate.
NAND cells are laid out in rows or strings by being connected end-to-end:
Strings typically have 32 or 64 cells in them. A string is connected at one end to a source line and at the other end to a bitline. A string is the minimum read unit. The string (bitline) and ground select transistors are control mechanisms at the ends of a bitline.
A page is a row of cells sharing a wordline, and has thousands of cells in it. A 4K page has 4,096 bytes, meaning 32,768 bits, with each bit being a NAND cell.
A block is a 2D matrix or array comprising pages (rows) and strings (columns).
A flash die has rows and columns of flash cells with the bitline providing horizontal connections to the cells and the wordlines having a vertical connection.
The diagram below shows a schematically simplified array of NAND cells with one horizontal row and a single horizontal column. The bitline and wordline connections are shown. The bitline and wordline do not come into contact with each other.
Let's now add in the other rows and columns to depict a 2D or planar array:
Moving onto 3D NAND means taking the individual NAND cells and flipping then into a perpendicular, or upright, orientation. In effect a bitline string is thus flipped upright, and that means the bitline has to run perpendicularly through the cell as well.
Devising that required a touch of genius from a Toshiba researcher, but we'll look at that in part 2. ®
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