Good gravy, Toshiba QLC flash chips are getting closer

Quadding 3D NAND cells to up capacity

Backgrounder Toshiba is pushing flash chip capacity higher on two fronts: through, er, Through Silicon Vias (TSVs) and by increasing a cell's bit count to four.

We covered the TSV notion here and now take a look at quadruple level cell (QLC) flash technology. Toshiba will present on this and TSVs in a keynote session at the August 8-11 Flash Memory Summit in Santa Clara (keynotes are from August 9-11).

The session abstract notes: "New technologies such as QLC (Quadruple Level Cell) BiCS FLASH offer high density, low-cost solutions, while TSV (Through Silicon Via) NAND offers high performance with significant power reduction."

To recap, BiCS stands for Bit Cost Scalable and is Toshiba and flash foundry partner WDC's approach to 3D NAND, the layering of ordinary or planer (2D) NAND chips atop each other. We have 48-layer cells in production and 64-layer ones coming with 96-layer and even 128-layer chips in prospect.

Progress beyond 64-layers has problems due to the difficulties in etching holes through the layers and so the TSV idea is to have two layers of layering: two 64-layer chips one on top of the other, with holes through them both, TSVs, for wiring to hold them together and carry out cell activity functions as well.

Flash cells can contain more than one bit. A single level cell (SLC) with one bit has two voltage states: 0 and 1. An MLC (multi-level cell or two bits) has four (00, 01, 10 and 11) and a TLC (Triple Level Cell or three bits) has eight. Thus a quadruple level cell has four bits and 16 voltage states.

Each time a bit is added to a cell, its capacity increases but its speed and write endurance lessen.

Manufacturers have decreased the size of flash cells so that more of them can fit on a standard-sized wafer and so increases flash chip capacity. Each time the cell geometry shrinks, then the write endurance decreases again. A table shows this, with cell geometry shrinking from 5x* through 3x, 2x to 1x, and the number of bits/cell increasing from one through two and three to four.

NAND_cell_table

This is an old table and doesn't reflect the beneficial effects of SSD controllers in increasing write cycles, or of over-provisioning SSDs with spare cells to replace ones that wear out. However, controller tech, such as error-checking and correction (ECC) and digital signal processing (DSP) can only increase write cycle counts so far. What this has meant in practice is that 2D TLC flash at 2x and 1x cell geometries hasn't been good enough for mainstream enterprise use, even with over-provisioning and sophisticated controller technology – as it doesn't last long enough.

A by-product of building 3D flash chips is that vendors have gone backwards in cell lithography terms and increased cell size to the 4x range, this increasing basic cell endurance. This has meant 3D TLC flash is now good enough for mainstream enterprise use. It also means QLC could become usable for applications needing read access to a lot of fast, relative to disk and tape, flash capacity but low write access. Archive data, on the active end of a spectrum of high-to-low archive access rates, is one such application.

Back in March, Jeff Ohshima, a Toshiba executive, presented on TSVs and QLC flash at the Non-Volatile Memory Workshop and suggested 88TB QLC 3D NAND SSDs with a 500 write cycle life could be put into production. The Flash Memory Summit keynote could add more colour to this.

Let's add a little bit of our own colour:

  • SanDisk was Toshiba's foundry partner. WDC has bought SanDisk and is continuing the partnership.
  • WDC subsidiary HGST has an Active Archive disk array using Amplidata object storage software.
  • SanDisk, now WDC, has its InfiniFlash all-flash JBOD equivalent with partners like Nexenta and Tegile providing software.
  • Pure Storage's FlashBlade development coud use QLC flash in 2018.

We can fit these dots together and conceive of QLC-based Active Archive and InfiniFlash products used as active archive storage devices offering fast access to old data for the retrieval of images and video clips, data sets, such as seismic and life sciences and critical surveillance data, for urgent analysis. This would be an assault on another part of the disk drive market.

Whether QLC-based active archive storage will come into production depends, amongst other things, upon cost, reliability and profitability. A foundry operator can make MLC, TLC or QLC chips from a wafer. Which are the most profitable? If QLC demand is low then it might not happen. However, if Toshiba (and WDC) see real demand out there then so will Samsung and Micron. Grateful storage array hardware and software vendors will have another weapon with which to fight hyper-convergence and even public cloud storage. The storage rollercoaster will have another ride added and pun-seeking journos will be able to say Quad erat demondstrandum. ®

* 5x refers to cell geometry of 59-50 nanometres per side. Thus 4x means 49-40nm and so on.

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