Etch a stretch: 3D NAND layer cake flop leads to 'string stacking'

String what-ting? Glad you asked...

Micron_16nm_NAND_wafer
Micron NAND wafer

Backgrounder Adding 3D NAND layers is butting up against aspect ratio limitations in the chip production process, which will limit the number of layers. String stacking is a technology that could provide an escape from this aspect ratio trap.

Samsung is shipping 48-layer 3D NAND, its third generation product; that’s the equivalent of 48 planar (2D) NAND dies layered one above the other. Micron and partner Intel have 32-layer 3D NAND. WDC/SanDisk and Toshiba are sampling a 48-layer chip, as is SK Hynix.

The 3D fab process does not just involve horizontal layering of 2D NAND but also the etching of holes – vertical channels – through the layers and here’s the issue. The equipment to etch these holes isn’t good enough once the layer count goes beyond 64.

According to Semiconductor Engineering, a 3D chip starts with a substrate, upon which chemical compounds are deposited using a vapour deposition process to build up NAND cell components. These deposited layers form wordlines, which connect rows of cells, and bit lines run horizontally in metallic layers across these deposited layers.

Bit lines are conceptually oriented at 900 to the wordlines and similarly connect a series or string of cells. Particular wordline-bitline intersections define cell addresses. In a 3D NAND die, there are also vertical strings running through the layers and connecting the bit lines. A Samsung 3D NAND chip can have up to 2.5 million such channels. Making these is the problem,

Once the layer deposition is complete, a mask is placed on the top and holes are laid out in it. Then an etching process is used to cut a channel through the underlying layers to the substrate. Existing material has to be removed to create the hole. The holes have to be precisely positioned and uniform in their dimensions; they mustn’t twist, taper or have sections which bow out, because that would make the die defective.

3D_NAND_etch_diagram

3D NAND etch schematic from Lam Research (PDF).

In terms of aspect ratio, the ratio of the vertical height to the channels’ width, current etching machine technology achieves between 30:1 and 40:1, sufficient for 32- and 48-layer chips. The coming 64-layer chips will need machines capable of etching holes with 60:1 to 70:1 aspect ratios, and they don’t exist yet.

Going beyond that, through 96 layers to 128-layer 3D NAND, will need far higher aspect ratios – like 110:1 to 120:1.

The NAND fabs can wait for etch machine technology to be developed, or shortcut this by stacking 3D dies, with two 64-layer dies forming a 128-layer chip in total, or two 48-layer dies forming a 96-layer chip overall. There is an insulating layer between the two dies and connecting wires, the bit strings, linking them, hence the term “string-stacking.” Theoretically you could stack more than two 3D dies.

It’s a potential way forward that provides more confidence 64-, 96- and 128-layer 3D NAND chips, with concomitant increases in capacity, are realistic steps on the 3D NAND capacity growth curve. ®




Biting the hand that feeds IT © 1998–2018