Flash dead end is deferred by TLC and 3D

Behold, data centre bods, the magical power of three

USB flash drive with NAND chip and controller chip

Comment The arrival of a flash dead-end is being delayed by two technologies, both involving the number three – three-level cell (TLC) flash and three-dimensional (3D) flash – with the combination promising much higher flash chip capacities.

As ever with semi-conductor technology, users want more data in the same space and faster access to it too, please.

Progress means making devices faster and denser: getting more transistors in flash dies, and hence more cells, with no access time penalty or shortened working life.

Flash data access can be speeded up by using PCIe NVMe interfaces, with several lanes active simultaneously, and so going faster than SAS or SATA disk-based interfaces.

It can also be hastened by putting the flash in memory DIMM slots, as SanDisk’s ULLtraDIMM product does using Diablo Technologies' intellectual property. However Diablo and SanDisk are involved in a legal case involving NetList alleging that they are using its intellectual property improperly. Now that's been resolved, with Netlist losing its case, flash DIMM technology can proceed.

But the core issue is flash chip capacity: how can we get denser chips and hence larger capacity SSDs?

With flash memory this has been achieved by adding a bit to the original single-level cell (SLC) flash, and by making the process geometry smaller.

It is currently in the 1X area, meaning cell sizes in the range of 19nm to 10nm. The smaller the cell, the fewer electrons there are and the more susceptible the cell is to leakage, error and influence from surrounding cells.

Smaller cells don’t last as long as larger cells as they sustain fewer write cycles. With 2-layer cell technology, called MLC, the cell stores two bits through two levels of charge and this adds to the process shrink problem.

It has been managed successfully with better error detection and the use of digital signal processing techniques by the flash controllers so weaker signals can be processed successfully with 2X-class flash (29-20nm cell geometry).

Shrink the process size to the 1X area, however, and the problems get worse the further below the 19nm level we get. Go below 10nm and they look insoluble. You can’t defeat physics.

What you can do is delay the entry into the cul-de-sac by reversing or stopping the process shrink train. You can increase the capacity of flash chips by adding a third bit with TLC NAND.

You can have another bite at the same cherry by layering existing planar – 2D – flash dies in a 3D way, stacking them one above the other to create much higher-capacity chips.

Charge detection

TLC technology has been around for some years. It gives an immediate 50 per cent increase in capacity over MLC flash – so why isn’t it popular in enterprise flash storage products?

A serious problem is detecting the level of charge in the cell. What happens is that there are eight possible levels, double the four levels of MLC flash, which is double the two levels of SLC flash. The table shows what is going on.

TLC flash state table

SLC, MLC and TLC state

SLC flash can have two levels of charge, or states, equivalent to binary 1 or 0. MLC adds a second bit to the SLC cell, meaning each SLC state can have two additional states, 0 or 1, giving us four states in total.

TLC flash goes one stage further, adding a third bit and therefore two additional states for each MLC state.

MLC and TLC flash state is worked out from the amount of current that passes through the cell, with a charge level corresponding to a state. However the intermediate charge levels have to be fitted between the cell’s minimum and maximum charge levels.

Having four states in this minimum-to-maximum spectrum is manageable, but detecting eight states reliably has proved problematic. The smaller the NAND process geometry, the worse this problem is.

Now let's look at what the flash manufacturers are doing.

Flash fabs and triple-level NAND

The main flash foundry operators, Intel-Micron, Samsung and SanDisk-Toshiba, are all active in TLC and 3D NAND developments.

With its low write cycle levels, TLC is generally seen as being suitable only for consumer flash devices such as camera cards and USB sticks. It is not yet considered usable in enterprises but that may be changing as controller tech develops and in conjunction with 3D flash.

Enterprise server-side and storage array solid state storage uses planar (2D) MLC flash. Although SanDisk and Micron (and therefore Toshiba and Intel) agree that 3D NAND is coming, they see it as arriving only in 2016/2017 and say they can get capacity increases from driving 2D technology hard.

Certainly SanDisk’s InfiniFlash solid state array, with 512TB inside its 3U rack mount casing, demonstrates what can be done with flash packing density, and is well ahead of any other flash array product in that metric.

NetApp has also said that TLC flash will play a role in its developing FlashRay all-flash array. SanDisk says its 512TB InfiniFlash product will embrace TLC flash, nominally giving it a 750GB maximum capacity.

We can be certain that TLC flash is coming to enterprise storage and can expect its arrival next year. Coincidentally, 3D technology could arrive at roughly the same time.

Third dimension

Developing 3D NAND for enterprise use, with requirements for reliable speed, data integrity and device endurance, brings additional problems.

Manufacturing the dies becomes more difficult the more layers there are, as vertical constructs such as trenches through the layers have extremely fine manufacturing tolerances.

As IBM Fellow Andy Walls from the Almaden Research Centre points out, 2D NAND cells have to counter sideways interference from surrounding cells.

With 3D NAND the interference can come from above and below as well as the sides, meaning cell insulation becomes more important. It is no simple matter to add more and more layers – 32, then 64, then 128. But these are easier problems to solve than getting sub-10nm flash cells working properly.

Samsung is leading developments here with its V-NAND devices, SSDs with 32-layer 3D chips. These don't use 1X-class NAND, having stepped back to 4X (49nm - 40nm) or 3X (39nm - 30nm) process geometries.

What Samsung loses in capacity with less dense planar technology, it more than makes up for with 3D layering, gaining endurance from the larger cell sizes and capacity from the layering. It has already introduced consumer-class SSDs using this technology.

The 850 PRO solid state drive uses Samsung’s 32-layer V-NAND technology with MLC flash, while its 850 EVO has 32 layers of TLC flash and up to 1TB of capacity.

The EVO has a five-year warranty, which inspires confidence that raw TLC endurance limitations have been overcome.

Samsung 850 EVO 1TB SSD

Samsung 850 EVO 3D NAND drive with TLC flash,

The other main flash foundry operators, SanDisk/Toshiba and Micron/Intel, are also energetic in 3D NAND developments. However, both see the timing of 3D NAND product introduction as being dictated not just by process maturity – how well and reliably they can make the stuff – but also by profitability concerns.

Take a 512Gb flash die made in with a 16nm planar (2D) process and an equivalent one made with a 3D process and there are three questions:

  • How will they be priced?
  • What will be the cost of producing them?
  • How much profit does each yield?

SanDisk and Micron contend that they will make more profit from building planar NAND than equivalent 3D NAND products at the moment. When the profits from 2D NAND start declining and the 3D NAND profit line crosses over it then the two will press the production start button.

Toshiba p-BiCS flash

SanDisk P-BiCS 3D NAND concept

SanDisk sees its P-BiCS process being used to build product in 2016, possibly earlier.

Intel says it will have a 3D NAND chip using Micron flash in 2016. The technology features;

  • 32 planar layers (with, we think, a 3X class process)
  • Four billion interconnect pillars between the layers
  • 256Gb – 32GB – of capacity in an MLC die
  • 384Gb – 48GB – in a TLC die,

BY using this technology Intel anticipates a 10TB SSD coming in late 2016 early 2017.

Crystal ball

If we take a step backwards from 3D specifics and look at what is likely to happen in the next few years we can expect TLC flash to appear increasingly in enterprise products this year and in 2016.

More 3D flash products will appear in 2016/2017 as Micron, Intel and SanDisk bring out their 3D products. These are likely to involve both MLC and TLC flash.

Let’s assume that these 3D and TLC products can become enterprise class with, say, capacities of 1TB for 4x-class geometry. Back-of-the-envelope math says 3x-class NAND will give us 2TB, with 2x-class NAND giving us 3TB-4TB, and then we reach the process shrink limit, around 10nm, again. What happens then?

An alternative non-volatile memory technology, such as PCM, RRAM or STT-RAM will probably have to be used because flash really will be in a dead end then, unless QLC (quad-level cell or 4bits per cell with 16 states and charge levels to detect) provides a third as much capacity as TLC flash and defers the problem for another couple of years.

But then flash really will have reached the end of the road. The post-NAND topic is explored in a second article. ®

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