Chipzilla spawns 60-core, six-teraflop Xeon Phi MONSTER CHIP
Every number for every feature is BIG and SCARY in Intel's new HPC HELLSPAWN
Intel has set some rumours to rest, giving a media and analyst briefing outlining details of its coming 60-plus core Knights Landing Xeon Phi chip.
Opening the bag to let the cat see a little bit of light, Intel has told journalists at a briefing at its Hillsboro, Oregon fab that the “honking big die” for the Knights Landing Phi hosts a knockout eight billion transistors.
As Timothy Prickett-Morgan reveals over at our sister site The Platform, Knights Landing's Silvermont Atom core will have all the instructions of a Broadwell core except for the closed-for-repairs TSX transactional memory feature.
Chipzilla is still holding to its 3 teraflops target for Knights Landing, and for single-precision floating point it's now touting 6 teraflops.
The company's staying coy about the maximum number of cores the chips will support, beyond the 60 it's owned up to, but it's rumoured that there'll be as many as 72.
There will be a coprocessor variant of the device, The Platform notes, and a version with 100Gb/second Omni-Path ports, the first Intel chip to sport the host fabric interface. With HPC applications in mind, Omni-Path supports the OpenFabrics Alliance (OFA) stack to provide compatibility with software written for InfiniBand and Intel's True Scale Fabric environments.
Intel will be hoping, however, that customers prefer Omni-Path's 100Gb/second, claimed lower latency, and planned 48 port switch chip over InfiniBand's 36 ports.
Six memory channels will support up to 64 GB per-stick of DDR4 memory – a total of 384 GB of far memory for the processor – and Intel is working with Micron to develop high-bandwidth memory for the chip, up to 16 GB per package.
The DDR4 memory will run at about 90 GB/second, with the local high-bandwidth memory able to run in the vicinity of 400 GB/second.
Peripheral communications will be handled by 36 PCIe 3.0 lanes. ®