Flash breaks free from the storage flat earth society

An exit route from the trap

Toshiba p-BiCS technology

NAND used to be the sole prerogative of a two-dimensional flat earth society obsessed with shrinkage, but that approach is running into a technological dead end.

To get more capacity the only feasible escape is upwards, using the third dimension and stacking layers of 2D flash to build multi-layered chips.

The dead end is happening because flash technology, driven by the need to persistently add more capacity in the same chip footprint as storage capacity demand rises, gets hit by a "one step forward, two steps back" syndrome.

This demand is real. Application working-set sizes, the data that should be in memory, are rising as in-memory processing of data is used to speed applications such as SAP, which require a high level of database access – hence SAP HANA.

Having an all-DRAM in-memory system is expensive. Adulterating the memory with flash trades off lower cost against slightly slower data access, and this is becoming more popular as flash chip density rises and its cost per GB falls.

Also, Big Data analytics requires clusters of compute nodes working in parallel to churn through petabytes of data. Using lots of flash to hold the data speeds the analytics a great deal compared with using disk.

These two use cases and others are expected to continue driving the need for denser flash memory, but there is a flash scaling trap approaching.

Incredible shrinking access

As the cell size decreases cell geometry step by step down to and below 20nm the speed of access decreases, the likelihood of read errors goes up and the ability of the flash to withstand re-writes decreases, shortening its working life or endurance.

Rising error counts can be dealt with by better controller software, and the shorter life can be countered by having more spare cells ready to use when other cells wear out and die. However, this means the error-checking and correction (ECC) logic becomes more and more complex and the number of cells needed for over-provisioning rises to an unconscionable level.

At that point it is more cost effective, and profitable, to make 3D NAND. Manufacturers have different perspectives on when this point is reached, depending on their own view of 2D NAND technology development problems and costs.

Typically the 3D chips we see today don’t use 2X or 1X-class cell size geometries, preferring to use 4X type cells, trading off some capacity against a lower error rate and greater endurance.

Also the manufacturers are pushing the manufacturing process envelope with 3D chips, and it makes sense to use cell lithographies that are tried and tested rather than leading edge.

NAND threesome

Most NAND sold today is multi-level cell (MLC) format, meaning 2bits per cell. But TLC (triple-level cell) NAND can be used too, even though at any cell geometry size TLC NAND has a shorter working life than MLC NAND. Naturally, the use case would be for read-intensive work than than write-intensive applications.

Where MLC 3D NAND could provide a doubling or tripling of capacity, TLC 3D NAND could provide a 50 per cent jump on top if that. Thus a 20TB MLC 3D NAND product could become a 30TB TLC 3D NAND product. We can imagine the mouths of flash-capacity junkies watering at this.

3D NAND available currently is in solid-state disk (SSD) format, geared to fit in 2.5in drive bays in servers and storage arrays. However a chip is a chip is a chip, and just like MLC NAND chips we can suppose that 3D NAND will spread to all flash formats, such as M2-format drives, PCIe cards, and even flashDIMMs, chips interfaced to DIMM sockets on server motherboards.

Currently SanDisk supplies 200GB to 400GB ULLtraDIMMs using 19nm MLC flash. We might envisage 1TB to 1.5TB versions in two to three years, which would signal a huge increase in effective usable memory resource by servers.

The PCIe flash capacity jump could be just as dramatic. Memblaze has recently announced a4 .8TB PCIe flash card using 2D NAND, while Samsung has a 3.2TB NVMe PCIe SSD using its 3D V-NAND technology.

These capacities could be doubled and tripled with 3D NAND chips. The same effect should play out with all-flash arrays. An HP StoreServ 7450 with up to 460TB of capacity currently could rise to 920TGB or even 1.4PB.

This is just our speculation by the way; we are not privy to any suppliers’ plans.

What is the state of 3D NAND play with the manufacturers?

Next page: Samsung and V-NAND

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