Better late than never: Monster 15-core Xeon chips let loose by Intel
New mission-critical CPUs are mission-critical to Chipzilla's critical money-making mission
With little power comes great responsibility
Also unsurprising is that the Xeon E7 v2 is more power-efficient than its predecessor – after all, the Westmere Xeon E7 was baked in a 32nm planar process, while the new Ivy Bridge Xeon E7 v2 is based on Intel's 22nm Tri-Gate process.
There are other power assists in the new chip as well, including running average power limiting (RAPL) at the socket and DRAM levels, a power-management feature introduced by Intel in the Sandy Bridge generation – which, remember, is the Xeon E7 generation that Intel skipped over.
Esmer also said that the Xeon E7 v2 has significantly lower idle power – as low as around two-thirds the idle power than a comparable four-socket Westmere-based system. In the data centers into which these babies will be installed, they'll rarely be left idling, but even when Esmer's exemplary Westmere and Ivy Bridge systems are cranked up to consume equal amounts of power, the Xeon E7 v2 will provide 40 per cent more system throughput than its predecessor. Or so we were told.
Seeing as how the Xeon E7 v2's target markets include "mission critical" data-center servers and HPC installations, it stands to reason that RAS (reliability, accessibility, and serviceability) features would be on the minds of the chips' designers – and it appears that they were.
In addition to the RAS features already in the current Xeon E7 line (PDF), Intel has upgraded the new chips' machine check architecture (MCA) and PCIe live error recovery (LER) capabilities – although the latter relies on OEM implementation.
RAS has always been something that the RISC chips found in data centers and HPC implementations did better than Intel's x86 chippery: those expensive, powerful chips have traditionally been better equipped for mission-critical applications.
Intel, however, has been inching up on those RISC chips in terms of RAS capabilities, one generation at a time. In fact, this time out even Intel's marketing folks are getting into the act, contributing what they do best: a new moniker. Meet the Xeon E7 v2 line's "Run Sure Technology".
RAS is not the only area in which Intel's x86 server chips are increasingly successfully when competing against their RISC rivals, said Intel's global enterprise segment marketing manager for the datacenter group Sajid Khan at the Xeon E7 v2 prebriefing. The new hotness: Chipzilla is raking in more mazuma.
In the past decade, Khan said, x86 chips have risen from under 20 per cent of the four-socket market revenue to virtual parity with the RISC/mainframe systems.
These are just revenue figures – x86's market-share lead is around 4X, Intel says (click to enlarge)
What originally fueled that rise, Khan said, was price: x86 chips were significantly less expensive than their RISC counterparts – and they still are, in most cases. The performance of x86 chips, however, lagged behind classic server RISC and mainframe processors until recently, he said.
When parts based on Intel's Nehalem architecture appeared in this market in 2011 in the form of the 32nm Westmere chips, Khan said, the x86 price advantage was joined by another advantage. "Across multiple performance benchmarks, we started taking leadership positions," he told us. "So it wasn't just about pricing, it wasn't just about price/performance – which at the outset was our strong point – it was about raw performance, as well, across multiple benchmarks."
In 2013, he said, these advantages raised revenues of x86-based four-socket-and-above systems to around 46 per cent of total revenues in the mission-critical space. Due to x86 systems being cheaper than their RISC-based and mainframe competition, however, that 46 per cent revenue share translated to a market share of around 80 per cent, up from Kahn's 2003 baseline, when x86 essentially split the market volume 50/50 with RISC-based and mainframe systems.
With a current mission-critical market-share split of 80/20, you might think that the transition is pretty much complete. Kahn would agree with you, but only to a point. "We believe a good chunk of that has happened – it's continuing, though," he said. "There's that continued momentum to move mission-critical environments away from RISC and Unix and onto Xeon and primarily Linux-based platforms."
Khan was more than happy to offer a couple of examples as to why it x86 chips were trouncing its rivals, comparing SPEC CPU2006 benchmark results – SPECint_rate_base2006 numbers, specifically – from tests of the IBM Power 750 Express, Oracle Sparc T5-4, and Intel Xeon E7-4890 v2 in four-socket systems.
According to Khan, not only did Intel's new mission-critical processors whip the competition, they did so despite costing less on a full-system basis:
Intel's marketing says butt is being truly kicked; click here for test details (click to enlarge)
Of course, affordable high-performance computing is all well and good, but in mission-critical applications, the ability to remain up and running without failure is also a, well, mission-critical consideration.
Khan was ready for those questions as well, with data from three surveys – not scientific testing, mind you, just surveys – conducted by Information Technology Intelligence Consulting (ITIC).
When comparing the results of the ITIC's 2013 survey with those conducted in 2009 and 2012, a clear pattern emerged: x86 systems are now in the major-league uptime ballpark.
In fact, according to those admins and C-level execs who participated in the survey, even Windows Server – which stunk up the place relative to AIX and Solaris in 2009 – now has a better uptime percentage than does Solaris:
The variances are, of course, minuscule, being in the range of thousandths or even ten-thousandths of a percentage point, but the implication is clear. "The data speaks for itself," Khan said, noting that not only have x86 systems running Linux-powered Suse SLES and Red Hat RHEL, along with Microsoft Windows Server, passed Oracle Solaris, but Suse SLES – according to those surveyed, at least – has an annual uptime only 0.0004 per cent less than that of the champ, IBM AIX.
Of course, as Kahn freely admitted, this ITIC study is hardly scientific, based as it is on a survey rather than on cold, hard, objective data. That said, if his earlier contention that a Xeon E7 v2–based system can outperform a four-socket Sparc T5-4 by 1.28x at a savings of "up to" 61 per cent, Oracle-based systems don't look all that compelling.
Khan also trotted out three case studies of companies that have standardized on Intel for mission-critical applications: one private-cloud migration conducted by Veyance, a second being a services switcheroo featuring Moody's, and a third investigating business-intelligence TCO involving Essar. Understandably, seeing as how these studies became part of Khan's presentation the companies had glowing things to say about their experiences – but they do provide some interesting reading, in any case.
So do many other features of the Xeon E7 v2 series that was announced this Tuesday at a press event at the Exploratorium museum of science and art in San Francisco. Their latency-reducing speculative snooping, for example, or some of the new RAS features in the fluffily named Run Sure Technology. But for this article, at least, enough is enough – we're well into TL;DR territory.
Rather than nattering on, we'll leave you with one quick comment that an Intel staffer made at the Xeon E7 v2 prebriefing – which just happened to be on the same day that his company announced its Q4 2013 financial results – that shed some light on the importance of the mission-critical chip series to Chipzilla's success.
One reporter asked him what high-end Xeons contribute to the earnings as expressed in the financial report. "Oh, a lot," he responded. "We are the bottom line." ®