Diablo trousers $28m to create a flash-in-the-DRAM technology
Mix me a storage cocktail, barkeep - but hold the fab
Diablo Technologies, a Canadian start-up founded 10 years ago, has just been given $28m to develop its flash-based in-memory technology.
The MemoryChannel Storage technology involves fusing flash and DRAM together, with executing apps getting fast access to data in both DRAM and NAND through the memory subsystem - think storage memory. Diablo claims the MCS tech, a memory channel-based solid-state storage platform, will provide extremely low latency and very high throughput, while avoiding the need for buying in excess flash capacity.
The MCS technology includes hardware with a chipset and software.
The fabless semi-conductor manufacturer was founded by CEO Riccardo Badalone, an ex-Nortel ASIC guy and originally Diablo's CRO, along with Michael Parziale, VP for business ops, previously the research and development VP, and another ex-Nortel man. The third co-founder is Franco Forlini, VP for strategic customer engineering, and ex-BroadTel Communications.
Diablo's CTO is now Maher Amer, an ASIC expert. With his help, Diablo has previously developed an advanced memory buffer and a plug-and-play Load Reduction chipset for DDR3 memory channels. The company claims to "have enhanced the performance and capability of server memory sub-systems across multiple generations of DRAM technology."
MCS uses flash now but has been designed for future non-volatile memory technologies. It will, Diablo says, "enable substantial improvements in transaction processing and data analysis within compute-servers, enterprise data centres and cloud-computing facilities worldwide."
This technology looks to have similarities to Fusion-io's ioMemory PCIe flash cards, its Virtual Storage Layer and its cut-through memory architecture for bypassing a host OS' disk I/O subsystem.
Diablo states; "Our customers are international Tier1 OEMs that integrate our advanced solutions in high-performance enterprise and data centre applications."
The $28m is a C-round funding exercise. A B-round in June 2008 netted $15m after the advanced memory buffer was developed - and paid for, we think, by the Load Reduction chipset development.
The target tier 1 OEMs for this diabolical flash in-memory technology are easy to identify: Cisco, Dell, EMC, HDS, HP, IBM and NetApp. Let's see which ones jump. ®