Intel puts cloud on single megachip
One die, 48 cores
Intel's research team has unveiled a 48-core processor that it claims will usher in a new era of "immersive, social, and perceptive" computing by putting datacenter-style integration on a single chip.
And, no, it's not the long-awaited CPU-GPU mashup, Larrabee. This processor, formerly code-named Rock Creek and now known by the more au courant moniker of Single-chip Cloud Computer (SCC), is a research item only.
As Intel CTO Justin Rattner emphasized during his presentation (PDF) on Wednesday to reporters in San Francisco, "This is not a product. It never will be a product." But the SCC does provide an insight into the direction into which Intel is heading - and the path the company is treading is many-cored.
Rattner characterized the many-core future to be "more perceptive," saying that "The machines we build will be capable of understanding the world around them much as we do as humans. The will see, and they will hear, they will probablly speak, and do a number of other things that resemble human-like capabilities. And they will demand, as a result, very substantial computing capability."
Not just 48 cores - 48 Intel Architecture cores
But the ancestor of those future chips, the SCC, is up and running today - as Rattner proudly pointed out while displaying a multi-die manufacuring wafer. "We're beyond the wafer level. [We have] packaged and running parts. This is not the typical Intel 'flash the wafer and then wait six months'."
While a move from 80 to 48 cores may seem like a step backwards, the SCC has one massive advantage over Polaris: its cores are fully IA-compliant. Polaris was a specialized beast, purely a proof-of-concept part. The SCC, by contrast, can do actual work - which Rattner and his crew proudly demoed.
One of the demos pointed directly towards the SCC's practical focus: Hadoop's Mahout machine-learning tools running an object-categorization task on the SCC with only minimal tweaking. As Mike Ryan, a software engineer from Intel Research Pittsburgh, explained to The Reg, "I didn't have to change any software. The only thing I had to do was permute some of the memory-configuration options as well as well as the distributed file-system options."
In other words, the SCC ran off-the-shelf, real-world software thanks to its IA compliance, and functioned in the Hadoop demo as a datacenter-on-a-chip. "The move to Intel Architecture–compatible cores gives us an opportunity to make more ambitious efforts on the programming side," Rattner said.
At 567mm2 and 1.3 billion transitors, the SCC is a hefty chip, but Rattner claims that as its performance scales - both frequency and voltage can be tweaked in real time - the SCC dissipates between 25 and 125W.
The SCC's 48 IA-32 cores were described by Rattner as "Pentium-class cores that are simple, in-order designs and not sophisticated out-of-order processors you see in the production-processor families - more on the order of an Atom-like core design as opposed to a Nehalem-class design."
Tech specs for the 45nm CMOS high-k metal gate part include four DDR3 channels in a 6-by-4 2D-mesh network. The cores communicate by means of a software-configurable message-passing scheme using 384KB of on-die shared memory.
The SCC was designed by a 40-person research team of collaborating software and hardware engineers with members in Braunschweig, Germany; Bangalore, India; and Hillsboro, Oregon. As Rattner joked, "Not only did we manage to do somewhat over a billion transistors, but we did it on three continents in time zones that are roughly 10 to 12 hours apart - in one sense, somebody was working on it 24 hours a day."
Perhaps some day in the many-core future, those 40 engineers will be supplemented by seeing, hearing, and speaking computing assistants with "human-like capabilities." ®