Hot Chips The multi-core chip revolution advanced this week with the emergence of Tilera - a start-up using so-called mesh processor designs to go after the networking and multimedia markets.
The Silicon Valley-based start-up's first product links together 64 RISC-like cores running at up to 1.0GHz. The real magic, however, stems from the five-lane switches used to link each core in an 8X8 grid that provides up to 32 terabits per second of data bandwidth across the whole chip. You end up with a product - Tile64 - that can tear through software threads.
Tilera looks to go after the FPGAs and DSPs used today in embedded devices, claiming performance, performance per watt and programming edges over rivals. For example, Tilera expects its chip to appear in security appliances that want to handle more-detailed analysis on packets, routers, surveillance DVRs (digital video recorders), video conferencing systems and boxes for encoding high definition video.
Unlike most start-ups that start telling the world how great they are before having product or customers, Tilera already has a solid story. Using a 90nm manufacturing process, TSMC is pumping out product for the company, which is then going into the hands of customers such as 3Com, GoBackTV and Codian. Tilera has ten customers in all, and products based on its chip should appear next year.
The mesh concept serves as a replacement for some of today's processors that require a central bus to manage data traffic. Some companies have moved past the bus concept, in AMD's case by creating its own high-speed interconnect called Hypertransport. Tilera extends that work by giving each core - or tile - five, independent networking lanes.
Intel has talked up a similar product when showing an 80-core demo unit over the past year. The chipmaker, however, does not expect to get out a trial product with x86 cores until next year, and who knows when it will actually ship commercial product.
In the meantime, Tilera claims that the Tile64 chip shows a 30X performance per watt and a 10X performance per sq. inch edge over dual-core Xeons. More importantly for Tilera's target markets, Tile64 has a 10X performance per sq. inch edge over TI's DM648 DSP, according to the start-up.
Tilera founder and CTO Anant Agarwal has assured us that programming for the Tile64 unit is within the reach of the average customer and notes that existing code written in C will run on the 32-bit Tile64 chip.
"If you have an application written for any multi-core or single processor architecture that's written to work with Linux, you can take it, compile it and have it running on our chip in minutes," he said. "Now, if you want to ratchet up the performance, we provide libraries and interface mechanisms that customers can use to tune code."
This process should prove easier than throwing out existing single-threaded code in favor of a parallelized rewrite or writing software for complex FPGAs, according to Agarwal.
Members of Tilera's team have roots that stretch to the first MIPS chip, MIT and Sun Microsystems' Sparcle chip and, of course, DEC's Alpha chip.
The 64-person company sells its chip to customers along with a TILExpress appliance card that plugs into PCI Express slots. You can see customers using this card as an accelerator in existing systems.
In the coming years, Tilera expects to ship products with hundreds and even thousands of cores if the market shows demand for such kit.
You can have a peek at the processor design here. ®
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