Intel Hyper-threading to return with 45nm 'Nehalem'

Intel's next major processor architecture, the 45nm 'Nehalem', will see the re-introduction of the chip maker's Hyper-threading simultaneous multi-threading technology, the company confirmed today. Nehalem chips will also feature an integrated memory controller and a graphics core.

Nehalem is due to go into initial production in 2008 and builds on the 45nm Core 2 architecture revision, 'Penryn', that Intel is due to put into volume production later this year. Penryn incorporates more advanced power management and fourth-generation SSE multimedia extensions, and these will appear in Nehalem too, and extended.

Hyper-threading Technology (HT) will allow each core within a Nehalem processor to appear as a pair of virtual cores, essentially by utilising otherwise unneeded instruction execution units. The result isn't a doubling of performance - HT only works well when the second thread will fit into the execution units not required by the first thread.

Intel suggested Nehalem-generation processors will contain up to eight cores, allowing them to process up to 16 threads simultaneously, with that thread suitability caveat applying, of course. The architecture's core-level dynamic power management system will extend to caches and operate at a thread level, suggesting that any still unused execution units can be temporarily powered down.

The chip maker has been hinting at adding an integrated memory controller to processors for some years, and it looks like that will finally take place with Nehalem. Interestingly, like the on-board graphics core, the integrated memory controller is "optional", for which read that they won't appear in all Nehalem-generation processors.

The GPU, for example, will appear in products aimed at mainstream users, so don't expect to see one inside a Nehalem-era Core 2 Extreme, for example.

Both elements will increase the bandwidth required between the CPU and the rest of the system, and Intel revealed Nehalem chips will see the introduction of a serial, point-to-point system bus. AMD's had one of these for some time - as, indeed, it's had on-board memory controllers. It uses HyperTransport. Intel didn't say which technology it will be using, but it did say the interconnect will be "scalable and configurable", presumably to cater for CPUs with a memory controller and GPU, and those without.