Intel fabs 80-core teraflop processor
Proof of concept
IDF Quad-core? Pah! Intel has produced an 80-core chip, the world's first programmable microprocessor with teraflop performance capabilities, the chip giant claimed today. It's not compatible with the x86 instruction set - it's a proof of concept part designed to show how a production processor might operate.
The monster part incorporates not only the usual data-processing facilities - essentially they're just floating point maths co-processors - but also features a network processing unit on each core to control core-to-core communication. The cores are linked in a mesh configuration.
Each core's designed to be clocked to 3.1GHz and is mounted with 20MB of SRAM stacked up on top of the die. Connecting memory this way provides an aggregate bandwidth of a trillion bytes per second, Intel said.
Once Intel boffins have worked out the best way to interconnect cores, memory and other processing features such as specific protocol handles and maybe even graphics engines, they will have to determine how the whole thing can operate with real CPU cores instead of the test units.
Still, Intel CEO Paul Otellini reckons such a processor might become commercially available in five years' time. That's out in the 32nm era, according to Intel's process roadmap. ®
Read Reg Hardware's complete IDF Fall 06 coverage here