Processors and semiconductors

No execute

AMD also began touting its chips' ability to block the execution of code stored in memory reserved solely for data. The functionality has been there for some time, but Windows XP Service Pack 2 - which shipped in the summer - at last gave AMD a good reason to shout about it.

Ditto Transmeta, which pledged in May to incorporate the technology into Efficeon, its 90nm processor. Efficeon shipped "in limited numbers", but won't appear in volume until next year, when an updated version, capable of attaining 2GHz, sporting the second generation of the company's LongRun power conservation technology and incorporating the new, SSE 3 instructions Intel debuted with Prescott, ships.

Freescale's 90nm PowerPC G4-class MPC7448, announced in Q3 2004, will sample in H1 2005, with the dual-core, e600-based MPC8641D sampling H2 2005.

The Athlon 64's 'no execute' support got into trouble with the Dutch advertising agency recently. Intel simply drew fire from AMD fanboys for adopting the technology, adding the feature to a new core stepping, E-0. This was announced in June but did not arrive until Q4, most notably in the 3.8GHz P4 570J. Intel announced plans to update the Mobile P4 and 'Nocona' Xeon lines with the E-0 core.

Intel's 64-bit x86

Nocona was better known as Intel's first 64-bit x86 chip. The source of considerable speculation - mostly over whether it was derived from AMD's AMD64 technology - Nocona was formally announced in February and shipped in June. Two months later, P4 processors equipped with EM64T - Intel's Extended Memory 64-bit Technology - arrived for the workstation and server markets.

EM64T is expected to debut on desktop P4s next year. So too will 'Sonoma', Intel's second generation of Centrino, after yet another rescheduling of a 2004 release, although some chipsets are now getting out the door, apparently. Intel nontheless announced Napa, aka 'Centrino 3', and began showing off the 65nm dual-core Pentium M, 'Yonah'. It also admitted the existence of 'Smithfield', the anciticipated dual-core P4. While stating that the part will be fabbed at 90nm, the chip maker wouldn't go so far as to say that it is a true 'one die, two cores' part, and not two separate Prescott cores stitched together.

AMD's dual-core strategy calls for the debut of desktop dualies in the second half of 2005, with Opteron versions arriving "mid-2005", around the time Smithfield is due to arrive. Initial dual-core AMD parts will almost certainly be fabbed at 90nm - AMD reckons volume 65nm production will take place sometime in 2006.

Even so, it's still expected to boost its market share next year as Intel faces the results of 2004's tribulations. However, nalysts warn that competition will be fiercer come 2006.

Itanic

Intel launched a 9MB L3 cache version of its Itanium 2 processor, but the year also saw the chip's co-creator, HP, ship its Itanium team over to Intel and hand over responsibility for future Itanic development. HP accounts for 70 per cent of world Itanium server shipments, though it knocked IA-64 workstations on the head in September.

By contrast, AMD's Opteron finally won Sun's support - or at least its formal support; AMD-based boxes are said to have begun shipping in 2003 - and Dell got as close as it ever has to saying it will end its Intel-only policy and adopt Opteron. When it might actually happen, is another matter altogether. ®