Intel preps Xeon chipset with discrete memory manager

North Bridge, South Bridge and Memory Bridge parts

Intel's upcoming 'Twin Castle' chipset separates the memory controller from the North Bridge chip to yield a three-chip product rather than the usual two-chip set-up.

So claims Xbit Labs citing sources close to the chip giant.

Twin Castle is aimed at four-way and up multiprocessor servers running Xeon MP processors, in particular the upcoming 90nm 'Potomac' part, though that's not due until 2005.

Intel's motivation appears to be the creation of a core logic platform that can easily support a range of server processors and memory types - just bolt on your preferred memory controller, just as you add to the South Bridge whatever I/O preferences you have.

It also smoothes the way for the incorporation of the memory controller onto the processor, though at this stage there's nothing to suggest that Intel has such a tactic in mind.

At the very least, it should make the adoption of new memory technologies easier, allowing Intel to support new memory speeds without having to requalify the entire North Bridge. Adding extra chips ups the cost, of course, but not enough to worry the kind of folks already paying for four or more processors per box. ®

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