Transmeta to launch 1GHz Crusoe on 26 June
800MHz TM5800 expected at PC Expo too
Transmeta will officially launch its two newest Crusoes - the TM5500 and the TM5800 - at the end of the month at PC Expo.
So says the company's CTO, Dave Ditzel, in an interview with Asia BizTech.
Both parts will be fabbed at 0.13 micron - as anticipated - cutting the die size from 88sq mm to 55sq mm. Transmeta is reducing the core voltage range, too, from 1.1-1.6V to 0.9-1.3V. The 5500 contains 256KB of on-die L2 cache. The 5800's cache is 512KB.
Ditzel said the parts will operate at between 600MHz and 1GHz. Transmeta was telling OEMs almost a year ago that the 5800 would ship at 1GHz. It also pointed toward 1GHz in its IPO prospectus. The 5800 was originally to have shipped late 2000. At least, that's what the company was indicating to said OEMs. Come Spring 2001, and the ship date had slipped to the second half of 2001. At CeBit, Ditzel said the part's clock speed would be over 700MHz, but in various benchmark comparisons this time he referred to 5800s running at 800MHz and 1GHz.
So either it will ship at various clock speeds, or Transmeta still hasn't made up its mind yet.
At CeBit Ditzel also told The Register that both chips would sport version 4.2.0 of the company's code morphing software, and he reiterated that in the Asia BizTech piece. Current Crusoes are running version 4.1.7
Version 4.2.0 should boost performance by around 28 per cent, including an 11 per cent increase in clock speed, Ditzel claimed citing CPUmark99 benchmarks comparing a 600MHz TM5600 running 4.1.7 and a 667MHz 5600 running 4.2.0. The new code morphing software can cut core power consumption by 2-42 per cent.
Ditzel said the 5800 consumes 5.5W at 800MHz, rising to 7W at 1GHz. By comparison, a 667MHz 5600 consumes 6.4W.
Finally, Ditzel said Transmeta will offer a 256-bit core Crusoe next year - twice the size of today's 128-bit cores. A wee while back, we heard that said 256-bit part, codenamed Astro, will run at 1.4GHz while consuming only 0.5W. It is thought to contain 128KB of L1 cache and 2MB of on-die L2.
Meanwhile, the existing 128-bit core will be extended to include more Northbridge functionality on the die. ®
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