Intel Developer Forum We can't help but admire how Intel learns from its mistakes. Exactly two years ago, at the Intel Developer Forum at Palm Springs, a table of us European journalists were handed a Merced processor, from the very first wafer of Itanic, at an evening reception.

We remember the look of horror as an hour later the chip was returned rather the worse for wear, its ceramic packaging tested for durability with a chinagraph Chad and having been used as a makeshift Pink Floyd cover for rolling something dubious.

Wisely, then, Intel officials decided not to throw first cut McKinley into the animal cage. Chips were demonstrated, but at a safe distance.

We did get a glimmer more detail. McKinley systems will be built to a 0.18 micron process and ship in configurations of either 1.5MB or 3MB of on-chip cache with a 400MHz frontside bus. McKinley's successor Madison will be the same chipset and packaging but with 3 or 6MB of cache and built on a 0.13 micron process.

Sound familiar? Well it's exactly what this ancient roadmappi mundi explained, two and half years ago. Most of it had been made public at Microprocessor Forum even earlier.The cache sizes are news, but it's exactly as predicted, only two and a half years late.

Deerfield has been described as the Celeron of IA-64. Which is one way of looking at it, we guess. Another, which Intel confirmed yesterday, is that the Itanic is so voluminous and power-hungry - requiring a 20A circuit - that only the ransacked Deerfield member of the IA-64 will conceivably fit into a a 1U or 2U rack. ®

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