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Articles about Tsv

Intel, Sun vet births fast, inexpensive 3D chip-stacking breakthrough

A startup headed up by former Intel chip architect, Sun Sparc CTO, and Transmeta cofounder David Ditzel has developed a way to allow communication in 3D stacked chips without the expense and fabrication hassles of creating physical connections between the layers. ThruChip Communications' ThruChip Interface (TCI) uses inductive …
Rik Myslewski, 21 Feb 2014
Comparison between ThruChip Communications' ThruChip Interface (TCI) and through-silicon via (TSV)

Semiconductor boffin: 3D NAND don't need NO STEENKIN' TSVs

Chip analyst Jim Handy of Objective Analysis took exception to several issues raised in a recent 3D NAND story, and El Reg storage desk asked him a few short questions for clarification. He provided a few short answers that did just that - and here they are. El Reg: Are there TSVs (through-silicon vias – vertical electrical …
Chris Mellor, 10 Jun 2014
The Register breaking news

Memory vendors pile on '3D' stacking standard

More memory responding faster in a smaller footprint: that's what chip vendors are hoping to achieve with the announcement of the HMC 1.0 specification. The standard, available here, sets down the specs for memory chip stacking using through-silicon vias (TSVs). In other words: individual memory dies, stacked vertically on top …

Intel teams with Micron on next-gen many-core Xeon Phi with 3D DRAM

Intel has released more details about its future "Knights Landing" Xeon Phi many-core processor, including a new high-speed interconnect tech called Intel Omni Scale Fabric, as well as on-package Micron Gen2 Hybrid Memory Cube (HMC) DRAM of up to 16GB. Intel presentation slide: what's new in Knights Landing Intel's Silvermont …
Rik Myslewski, 23 Jun 2014

Micron tears away cloak to reveal its Gen3 Hybrid Memory Cube

Micron has revealed some of the goals – and the manufacturing challenges it faces – for the development of its next-generation "all silicon" Hybrid Memory Cube (HMC). Micron's current HMC Gen2, engineering samples of which having been released this September, stacks up layers of memory cells, each on an organic laminate …
Rik Myslewski, 19 Oct 2013
hands waving dollar bills in the air

Samsung offers eco-econo green DRAM

Using through-silicon vias, Samsung is stacking its memory chips higher and reducing energy consumption. It has a 32GB double data rate-3 (DDR3) RDIMM (Registered Dual-Inline Memory Module) using these through-silicon vias (TSVs) to build this 3D chip. The process technology is 30nm and the RDIMM is built from 4Gbit DDR3 memory …
Chris Mellor, 18 Aug 2011
Micron HMC chip during manufacture

Micron: Our STACKED SILICON BEAUTY solves the DRAM problem

Dratted multi-core CPUs. DRAM is running into a bandwidth problem. More powerful CPUs has meant that more cores are trying to access a server’s memory and the bandwidth is running out. One solution is to stack DRAM in layers above a logic base layer and increase access speed to the resulting hybrid memory cubes (HMC), and Micron …
Chris Mellor, 27 Nov 2013
channel

Samsung readies less sockety servers for 3D stacked memory

Samsung has worked out a way to stack memory chips vertically, increasing memory density and decreasing power needs. It says next-generation servers are going to have fewer memory sockets – 30 per cent fewer – implying that unless you can stick more memory in a socket, you're going to have less of the stuff. What it's done is …
Chris Mellor, 07 Dec 2010
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Elpida aims to issue $1bn of paper to fund re-tooling

Elpida needs to raise nearly one billion dollars to fund a transition into making memory for smartphones and tablet PCs, relying less on PC DRAM in the future. Revenues from DRAM have fallen short of what's needed and Elpida will issue new shares and convertible bonds to pay for the direction change. It's a massive amount of …
Chris Mellor, 12 Jul 2011
server room

IBM, Micron tag team on 3D memory breakthrough

The Hybrid Memory Cube consortium formed by Samsung Electronics and Micron Technology this October is leveraging IBM Microelectronics' 3D wafer-baking expertise to get HMC memory to market in two years. IBM said on Thursday that it has come up with manufacturing breakthroughs to create the conduits that link stacked blocks of …
homeless man with sign

Samsung, Micron bake 3D chips for next-gen RAM

We're hitting a memory wall, if you didn't know, and processor cores are going to be held up because DRAM can't scale up enough or ship 'em data fast enough. Samsung and Micron aim to fix that with 3D memory cubes and a consortium to define an interface spec for them. Samsung and Micron, asserting that existing 2D DRAM …
Chris Mellor, 07 Oct 2011
SGI logo hardware close-up

New chippery on parade at ISSCC

The new year in IT always begins around now, when the IEEE puts out the advance program for the International Solid State Circuits Conference, which takes place in San Francisco in February. This time around, it runs from February 19 through 23, and while there are not a large number of server-class processors coming out, there …

3D processor-memory mashups take center stage

A trio of devices that stack layers of compute units and memory in a single chip to boost interconnect bandwidth were presented at this week's International Solid-State Circuits Conference in San Francisco. Sharing the stage at the ISSCC's High Performance Digital session were three technologies; one prototype developed by IBM …
Rik Myslewski, 24 Feb 2012

Samsung adopts latest 3D chip stack tech

First IBM, then Intel, now Samsung. The South Korean chip maker today said it too was going to implement the 'Through Silicon Via' (TSV) technique to allow it to stack layers of chip dice more efficiently. TSVs are tiny tubes drilled through a chip's silicon foundation and filled with metal and capped with connector bumps. The …
Tony Smith, 23 Apr 2007

Tosh talks up Flash chip stack tech

Toshiba has applied the through-silicon via (TSV) technique - chip makers' flavour-of-the-month technology - to boost the capacity of NAND Flash chips with only a "minimal" increase in chip size and no need for a new fabrication node. Announced today at the VLSI Symposium, held in Kyoto, Japan, Toshiba's new Flash structure …
Tony Smith, 12 Jun 2007