The PCI-SIG - the organisation behind the PCI Express - quietly released the base spec for version 3.0 of the bus standard.

PCIe 3.0 was originally due to be released in 2009, but in August of that year it was delayed until 2010, in order, it was said at the time, to ensure compatibility with PCIe 1 and 2.

Come January 2010, the spec was delayed again, and this and further announcements during the year saw the release put back to Q2, then H2 and, finally, Q4.

And here it is at last: a full description of "the PCI Express architecture, interconnect attributes, fabric management, and the programming interface required to design and build systems and peripherals", the PCI-SIG website says, in documents dated 10 November 2010.

The catch: you can only take a look if you're a PCI-SIG - SIG stands for Special Interest Group - if you have a special interest in the bus and have coughed up the membership fee to prove it.

PCIe 3.0 ups the bus' based clock to 8GHz from 2.0's 5GHz. A change to the bus' line coding system, from 8/10-bit to 128/130-bit further increases the amount of data that can be pumped down the PCI pipe every second. So while PCIe 2.0 can do 4bn transfers a second, PCIe 3.0 can do 8bn.

PCIe 3.0 controller chips and motherboards using them should be out next year. ®

Related story

• PCI organisation confirms PCIe 3.0 delay (21 August 2009)

  https://www.theregister.com/2009/08/21/pci_3_delay/