GlobalFoundries says Intel process squeezes chip devs
Future chips: extreme, ultraviolet & metal
GTC 2010 According to AMD-spinoff GlobalFoundries, chip-baking is about to hit a wall — but they're ready for it. They also claim that their way of handling the latest advance in chip materials is superior to that used by Intel and soon to be introduced by their ginormous competitor, TSMC.
On Wednesday at its first annual Global Technology Conference in Santa Clara, California, GlobalFoundries shared its plans with a few hundred of the world's chip designers, and spent the day explaining why GlobalFoundries is the chip-baker that they should trust with their futures.
The wall that chipmakers are rushing toward is the fact that wavelengths of light are too big for current lithographic techniques to continue to scale down effectively to be able to create tinier and tinier transitors. That's an oversimplification, of course, but you get the idea.
Gregg Bartlett, GlobalFoundries SVP for technology and R&D, told the conference attendees that the current high-end technique — known as 193nm immersion lithography and introduced at the 45nm node — is reaching its limit. "Today we sit on what is effectively the end of evolutionary changes for wavelength scaling," he said.
In a nutshell, there are two types of immersion lithography: single and double-patterning technology. Double patterning allows for smaller silicon features, but its notoriously complex and expensive. "Double-pattern immersion lithography will [be used] down to and including the 20nm technology node," Bartlett said, but due to significant complexity and cost challenges, the cost involved "effectively lowers the bar for alternate lithography schemes."
According to Bartlett, there are a few alternate schemes from which to choose:. "We do know that there is disruptive innovation that is now necessary to continue fueling the technology roadmap going forward. And there are multiple candidates out there such as multi-e-beam direct write, extreme ultraviolet lithography, and even nano-imprint lithography."
GlobalFoundries is betting on extreme ultraviolet lithography, better known among chip-bakers as EUV. "We really do see EUV squarely in our technology roadmap," Bartlett said.
But it's not a simple matter of swapping those double-pattern systems out of fabs and replacing them with EUV gear. "EUV is not without its share of challenges," Bartlett said, citing defect-free masks as one of the most significant problems, along with line-edge roughness at fine resolutions and EUV's hunger for power.
Bartlett noted that mask and line-edge improvements are underway, but that despite "several orders of magnitude improvement over the last decade," source power and throughput aren't yet at what he referred to as "the crossover point." He did, however, express satisfaction at the rate of progress.
And then there's that all-encompassing bugaboo, total cost of ownership. The fixed costs of a EUV installation are still more than double that of single-pattern immersion lithography, and slightly more than that of double-pattern immersion. It's in other areas — namely chemical and reticle costs, plus exposure expenses — where EUV is more cost-effective than double-pattern, according to Bartlett.
But moving to EUV has the distinct advantage of not requiring double patterning. "Because you can single-pattern [EUV]," Bartlett contends, "it actually offers a cost-reduction opportunity."
Over the past decade, he said, GlobalFoundries (as an arm of AMD) has made significant strides in EUV development. In 2008, for example, they accomplished their first full-field EUV patterning on a 45nm test chip, they've shipped more than 60 EUV masks from their mask-manufacturing facilities in Dresden, Germany, and the company "continues to lead" in solving the line-edge roughness problem.
Plans are now in place for GlobalFoundries to establish its first EUV-based production facility in the first half of 2012 at its Fab 8 facility in Saratoga County, New York, currently under construction and designed to produce 300mm wafers using 28nm and smaller process technologies. Bartlett said that volume production of EUV-etched wafers is planned for 2014 or 2015.
'Intel and TSMC have it backwards'
Lithography, however, isn't the only challenge facing designers of ever-shrinking process-node technologies. There's also the fact that as chip elements get smaller and smaller, current leakage at transistor gates can cause fatal problems — fatal to chip performance, that is.
The solution here is to use materials other than traditional polysilicon when building transistor gates — and Intel took an early lead in this sphere when it introduced its high-k metal gate technology in its 45nm "Penryn" line, launched in November 2007.
But there's more than one way to gain the low current-leakage advantages provided by high-k metal gate–based chips. Bartlett drew a distinction between the high-k metal-gate technology to be used by GlobalFoundries and that which is now employed by Intel and soon to be introduced by the Taiwanese chip-baking giant TSMC — although, as The Reg has noted before, GlobalFoundries and its allies in the joint development alliance (JDA) prefer the term "HKMG".
Stripped to its basics, the distinction is that the JDA chip-bakers use what's called a "gate-first" manufacturing process, while Intel and TSMC's process is "gate-last", also known as "gate-replacement". The first/last difference refers to at which point in the manufacturing process that the gate itself is created, and replacement refers to the technique used in its manufacturing.
Debate continues as to which method is preferable, but the arguments essentially boil down to the gate-first method being more in line with that of good ol' fashioned polysilicon-gate creation, and therefore simpler, more conducive to existing chip designs, and arguably more scalable.
The gate-last proponents concede that their method is more complex, but since it doesn't involve subjecting the gate material to high temperatures, designers have a wider range of materials from which to choose, allowing for better optimization. Intel also claims (PDF) that the gate-last scheme can be a boon to strained-silicon enhancements.
Bartlett, as might have been guessed, touted the advantages of gate-first HKMG technology. One major advantage, he claimed, is that the gate-first method not only can produce chips of comparable performance to that of gate-last chips, but can do so in a smaller-sized die. And, of course, the smaller the die, the greater the yield per wafer, and thus the lower the cost per chip.
What's more, a gate-first design doesn't require a massive redesign project, since the manufacturing process is similar to that of existing polysilicon-gate chips.
"The promise of a gate-first implementation is, in fact, a more flexible and a more traditional design style," Bartlett said. "It was our very clear, stated strategy to not force the implementation of a new material and a new design style upon our customer base. There's enough technical risk associated with just the introduction of high-k metal gate that trying to ask our customer base to completely change their approach to how they design products was not the right approach."
Playing to his audience of chip designers who were either GlobalFoundries customers or potential customers, Bartlett reminded them: "This really is the key point to a gate-first implementation for high-k metal gate: maintaining the same degree of flexibility. So we support bidirectional poly-routing, we support jogs, and those are things that many of you as customers can continue to do, versus a gate-last implementation where you can no longer do those things."
The cost savings are not insignificant, according to Barlett. "So how does that show up in the marketplace?" he asked rhetorically, then answered: "Well, it shows up in your P&L statement." Bartlett argued that over a four-year product cycle that would cost $500m in a gate-last implementation, GlobalFoundies' gate-first manufacturing could save its customers a cool $75m, simply by needing to run fewer wafers to produce the same number of chips.
Gate-last Intel, of course, is its own customer, and so the cost savings that might be experienced by a third-party customer of a gate-first foundry is not a prime motivator. Saving money is a wonderful thing, of course, but Intel has the luxury of using its gate-last scheme to tune and optimize its chipmaking as it sees fit, rather than to please its customers.
Semiconductor foundry TSMC, however, is a direct GlobalFoundries competitor. But Bartlett is confident: "Our 28 nanometer solution offers significant ... advantages over the gate-last that is available in the marketplace. First and foremost, [there is ] a 10 to 20 per cent die-scaling advantage and the consequent cost advantage that comes with that, as well as still addressing the performance and power-scaling that is desired."
And GlobalFoundries' 28nm, gate-first technology is coming soon, Bartlett said. "Risk production [will begin] in the fourth quarter of this year on the first version of the 28 nanometer." In addition: "We do anticipate, as a consequence of industry analysts, that this will be a leadership technology, not just from a performance and die-scaling advantage, but also [in terms] of global capacity across the JDA ecosystem."
Bartlett also touched on the next step after 28nm: "And our 20 nanometer is well underway. It is a full-node shrink, and we do have test chips running in our Fab 1 in Dresden today. We are deeply engaged with early-adopter customers and have design kits available."
It remains to be seen whether GlobalFoundries' approach can carve a significant chunk of business away from TSMC and other semiconductor foundries. But if Bartlett's financial arguments can be matched by process reliability and on-time production, the AMD spinoff may have — wait for it — a "fab" future. ®