Original URL: http://www.theregister.co.uk/2010/03/02/micron_sub25nm/
Micron to make even teenier NAND dies
25nm ain't small enough
Not content with shrinking its NAND flash process to 25nm, Micron is heading below that level next year.
We don't know exactly how small the NAND dies are going to get but DigiTimes reports Micron will get there next year. The company hasn't even started mass-producing its 25nm product yet and it's pretty advanced. As Micron says, 25nm is 3,000 times smaller than the diameter of a human hair.
The company is buying rival Numonyx and partnering with Intel in the IMFT flash fabrication operation.
With the 25nm process. Micron is planning to build 8GB flash dies, with 2 bits per cell. A sub-25nm process might make 16GB, 2bit per cell dies possible, doubling NAND product capacity.
SanDisk and Toshiba are reported to be getting ready to build 24nm NAND in the second half of this year, moving on from their current 32nm process, and slightly leap-frogging Micron's 25nm process. They'll have both 2 bits per cell and 3 bits per cell product.
Analysts think SanDisk and Toshiba see 3 bit multi-level cell (MLC) as their preferred route to increasing flash capacity whereas Micron and Intel think process shrinkage is better. However Micron will produce 3bit MLC product, thinking it could be useful for solid state drives (SSDs) rather than portable media players and the like.
Micron is working on adding EZ-NAND (Error Correction Code - ECC - Zero NAND) flash, in which the NAND product does the ECC work instead of the host controller, simplifying the job of host controller manufacturers. EZ-NAND is part of the Open NAND Flash Interface (ONFI) Working Group's 3.0 specification. This should, Micron hopes, make its flash better suited for portable and consumer electronics applications. It says its 25nm, 8GB flash product could store 2,000 songs or 7,000 photos.
The sub-25nm product could increase that to 4,000 songs or 14,000 photos.
The current Micron flash product uses floating-gate technology transistors but Micron may change this to a charge trap-based technology. A floating gate in such a die is surrounded by highly resistive materials so, once charged, it retains its charge. The charge trap idea is to change this to a sandwich of layers with the inner layer having its charge trapped between the other layers. This technology can be made at smaller dimensions than floating gate flash. ®