Original URL: http://www.theregister.co.uk/2010/02/01/imtf_25nm/
Intel and Micron get flash process lead
Shrinks to 25nm
Intel and Micron have jumped to a 25nm NAND flash process, shrinking cell size and raising wafer yields. They'll use their lead to raise profit margins instead of lowering prices.
The two companies manufacture flash chips through a joint-venture, Intel Micron Flash Technologies, 49 per cent owned by Intel and 51 per cent by Micron, and formed in 2006. Current IMFT flash uses a 34nm process and the new process shrinks this to 25nm. It is, IMFT says, the smallest NAND process, indeed the smallest semi-conductor process in the world.
25nm process flash die.
Intel said immersion lithography is required for some layers of the 25nm process, but is not disclosing which layers or how many.
IMFT is planning to build 8GB flash dies using this, with 2bits per cell as this gives, it says, the best balance between performance, capacity and reliability. A single bit cell would be faster but have half the capacity. A 3bit multi-level cell (MLC) would be slower and less reliable than the 2bit MLC design chosen, although it would have half as much capacity again. An 8GB flash die is small enough, at 167 square millimetres to pass through the central hole of a CD.
The new process supports the ONFi 2.2 source synchronous interface, delivering up to 200MB/sec in performance. ONFI 3.0 is under development and hit is hoped it will be faster at 400MT/sec (mega transfers per sec). This is thought to mean 400MB/sec (see summary slide). No timescales were provided.
With the 34nm process it would take 64 dies to produce a 256GB SSD (solid state drive) and that can now be done with half that number. Instead of reflecting the lower unit count with a price cut, IMFT say they will probably keep prices the same and so increase their profit margin.
Jim Handy of Objective Analysis reckons "At a die size of 167mm² a 300mm fab should be able to manufacture just over 400 dice per wafer. This gives a manufacturing cost of about $4.00 per chip, or $0.50/GB. Compare this to a more common 45nm MLC NAND on a 300mm line which should cost about $1.75/GB." He also thought it "allows [IMFT] to squeeze more gigabyte production out of their Lehi and Manassas lines before having to equip their new fab in Singapore."
Intel and Micron will also be able to introduce higher capacity models in their existing flash product lines. For example, Intel sells its X25M in 80GB and 160GB versions. It will be able to add a 320GB version. This has implications for storage companies such as Pillar and Avere, which use Intel SSDs in their storage products. It also means that the HitachiGST SSD - which is being developed using Intel technology - could benefit as well.
Intel could also use the new process technology for its Braidwood flash-on-the-motherboard technology.
Micron has its RealSSD C300 line, offering 128GB and 256GB flash, with a 6Gbit/s SAS interface, using the existing 34nm process. It could now add a 500GB high-end model.
The 25nm process is producing chips which are being sampled by OEMS and general availability is expected in the second quarter of this year. Intel suggested a 3bit MLC product could be built using the new process, notwithstanding the points listed above. Nothing was said about producing the fast SLC X25E product with a 25nm process.
It is expected that other flash foundries, such as those operated by Samsung and Toshiba, will transition to sub-30nm processes in the next six to twelve months. IMFT is on a 12-15 month refresh cycle for its flash process technology, with the 34nm process being introduced in May 2008, so we could expect a sub-20nm process to appear around July 2011. This may need a change from current floating gate cell technology to a charge trap memory design.
The announcement presentation included a slide on scaling NAND dies vertically, with three methods already developed for DRAM listed: Epitaxial TFT NAND; Vertical NAND string; and Polysilicon TFT NAND. Nothing was said about this, though. ®