Original URL: http://www.theregister.co.uk/2010/01/28/isscc_chip_preview/

ISSCC: Home cooking at the wafer bakers

Iron chefs chop their chips

By Timothy Prickett Morgan

Posted in Hardware, 28th January 2010 12:02 GMT

The semi-annual dance of chip technology previews gets its 2010 start at the International Solid State Circuits Conference in San Francisco two weeks from now, and Intel, Advanced Micro Devices, IBM, Sun Microsystems (soon to be a division of Oracle), and Hitachi are going to be talking up their future chip tech.

Intel's chip geeks will be showing off the company's "Westmere" family of 32 nanometer processors, which already made their debut earlier this month inside desktop and laptop machines and which are expected to come out for servers within the next couple of months. The details on the session being hosted by Intel at ISSCC are pretty skinny, as you can see from the advanced program. But the word on the street is that Intel will be showing off improvements to the QuickPath Interconnect and low-voltage DDR3 buffers added with the Westmere tweaks.

Intel is showing off another chip which is sure to raise some eyebrows. The company's chip design teams in the United States, India, and Germany have cooked up a 48-core, 32-bit x86 chip implemented in 45 nanometers. This chip, which implements a 2D mesh network in a six-by-four core array, uses message passing across a 384 KB on-die shared memory and also sports fine-grained power management through a feature called dynamic variable frequency scaling (DVFS), which allows individual cores to run at eight different voltages and 28 different frequencies. In the performance range Intel has set up for the chip, power dissipation for this baby x86 supercomputer cluster on a chip (well, that is essentially what it is) ranges from 25 to 125 watts.

Intel will also be discussing a streaming circuit switch, suitable for linking computing elements on a chip in an 8-by-8 2D mesh together, that is also implemented in 45 nanometers and that provides 4.1 Tb/sec bisections and 560 Gb/sec of aggregate bandwidth. This mesh network was cooked up in Intel's Hillsboro, Oregon, facility. This mesh network burns 4.73 watts at 1.1 volts and the network links can apparently be pushed up to 6.43 Tb/sec. No word on how this mesh network will be used by Intel.

Rival AMD will be showing off a new core design implemented in 32 nanometers using silicon-on insulator processes. This core, says the ISSCC abstract, will have more than 35 million transistors (excluding its L2 cache memories) and will crank its clocks up beyond 3 GHz. The AMD chip will have a power dissipation range of between 2.5 and 25 watts, including a zero-power gated state, and will be aimed at desktop and mobile computers. This core is very likely the one that will be launched in the Fusion family of processors, which will pack CPUs and GPUs on the same piece of silicon. (See El Reg's review of the AMD desktop and mobile roadmaps here.)

The engineers and designers from Sun will be showing off the future "Rainbow Falls" Sparc T series processor, a 16 core, 128-thread chip that will have six clock and four voltage settings to offer its own brand of fine-grained power management. The Rainbow Falls chip, which is due around the middle of this year for servers with one, two, and four sockets according to a Sun roadmap from June 2009 obtained by El Reg, will have a glueless means of connecting multiple chips together. The Rainbow Falls chip will be implemented in a 40 nanometer process, presumably by Texas Instruments, Sun's outgoing fab partner, and has an on-chip 6 MB L2 cache shared by the cores that sports 461 GB/sec and an on-chip SerDes I/O processor with 2.4 Tb/sec of bandwidth.

Big Blue will, as you might expect, show off its impending Power7 chip, which was highlighted at last summer's Hot Chips conference in Silicon Valley and further detailed by IBM at the SC09 supercomputing conference last November. As El Reg has reported previously, the Power7 chip is implemented in IBM's 45 nanometer SOI processes and sports eight cores (with four threads each) and 32 MB of embedded DRAM that is used as a shared L3 cache. The first Power7-based systems are expected to be announced sometime in February.

IBM's chip designers will be showing off another experimental Power7 derivative, an unnamed 2.3 GHz "wire-speed Power processor" that sports 16 cores and 64 threads. This chip will burn 50 per cent less power (compared to what, IBM doesn't say) and will dissipate 65 watts of heat running at 2 GHz at 0.85 volts. The chip includes eDRAM as the on-chip L3 cache, like the Power7 does, and this could very well be a future Power7+ chip that Big Blue is showing off. (Power4+, Power5+, and Power6+ were not particularly impressive, and IBM may be trying to demonstrate that it can tock as well as tick, to use the Intel lingo.)

Finally, Hitachi will be showing off a multicore chip implemented in 45 nanometer processes that has eight general purpose cores, four "dynamically reconfigurable processors," two 1,024-way matrix co-processors, and on chip peripherals and interfaces. Hitachi says this chip runs at 684 MHz and will deliver 37.3 billion operations per second per watt at 1.15 volts. ®