Big Blue murders Cell blade servers
Power chips live on. In game consoles
IBM's QSZ2 Cell-based blade server received nary a mention at last week's SC09 supercomputing trade show in Oregon. And for good reason.
Top brass in IBM's Systems and Technology Group killed the product off about 18 months ago, according to sources familiar with situation.
The QSZ2 blade server was slated to use a future version of the PowerXCell hybrid processor sporting two 64-bit Power cores and 32 of the synergistic processing element (SPE) co-processors that give the Cell chips their number-crunching and graphics processing power. But IBM never admitted it existed. So it's certainly not going to admit it has now ceased to exist.
"IBM, along with partners Sony and Toshiba, created the Cell processor and Cell technologies became a critical step in IBM’s hybrid and multicore computing strategy," explained Ron Favali, a spokesperson for IBM's Systems and Technology Group, in a statement.
"The Cell processor has had significant success in Sony's game console and cell technology served as the foundation for IBM's "Roadrunner" supercomputer, the first system to break the petaflop barrier and one of the most energy efficient systems in the world. Based on our experience gained from Cell, we now believe that the next generation of computing will rely heavily on the integration of multicore and hybrid technologies," Favali continued.
"IBM continues to invest in Cell technologies as part of this hybrid and multicore strategy, including in new Power7-based systems expected next year. IBM continues to manufacture the Cell processor for use by Sony in its PlayStation3 and we look forward to continue developing next-generation processors for the gaming market."
IBM has had several iterations of its Cell chips. The first was implemented in a 90 nanometer chip process and was baked at Big Blue's wafer factory in East Fishkill, New York, using the one Power core and eight SPE setup. In March 2007, the Cell chip was shrunk to a 65 nanometer process, and in February 2008, it was moved to a 45 nanometer process (a chip that Sony is now using in its latest PlayStation 3 Slim game console).
Later that year, the 65 nanometer version of the chip, dubbed the PowerXCell 8i, came out with significantly improved double-precision floating point math. It is this chip that is providing most of the math oomph for the Roadrunner massively parallel Opteron-Cell hybrid installed at Los Alamos National Laboratory.
The future Cell chip that was supposed to be integrated on the QS2Z blade was on roadmaps dating from 2007, when IBM was ramping up the idea of using Cell-based blades as co-processors for mainframe, RISC, and x64 servers. That blade was expected to pack two of the unnamed dual-core, 32 SPE Cell chips (calling it the Power2XCell 32i would have made sense, but El Reg has never seen that name anywhere) onto a single blade, yielding up 1 teraflops of double precision floating point performance (about 500 gigaflops per Cell complex) or about five times the current QS22 blades (and five times the PowerXCell 8i chip complex).
That is about as good as Nvidia is going to be able to deliver early next year with the "Fermi" Tesla 20 GPU co-processors. A single Fermi GPU with 512 cores will offer 520 or 630 gigaflops of performance, depending on the model.
The QSZ2 blade was slated for delivery in the first half of 2010, according to some old IBM roadmaps, but as I pointed out two months ago last month when Oak Ridge National Laboratory said it was going to embrace GPUs for future supers, Big Blue hasn't said anything about the QSZ2 for years - and certainly didn't want to talk about it last week.
According to sources that have the inside story, that's because the top brass in Systems and Technology Group, who were hell bent on making cuts in servers delivered, decided around 18 months ago that the Cell-based blades were not carrying their weight in terms of revenues and profits.
Los Alamos front
IBM was unwilling to confirm these rumors. But the rumors fit the data. There's a reason why Los Alamos, which has zillions of Cell processors and code that has been tuned to run on it, is fronting the Hybrid Core Consortium, which seeks to make it easier to program hybrid supercomputers using a mix of CPUs and co-processors and which wants to use the leverage of the big HPC centers in government and academia as well as software developers who write code for supers to compel companies to make certain technologies and support them based on the results they get in the field.
You can parse IBM's statement above in a number of different ways. First, Cell was a collaborative design by IBM, Sony, and Toshiba, and all three companies put hundreds of millions of dollars into the Cell design and the processes to make it. IBM has made billions of dollars making Cell chips and Sony has made its billions selling PlayStation 3 consoles; heaven knows what Toshiba has made, but the Cell chips are in TVs, apparently. If Sony wants a faster or different Cell chip, you can bet IBM will make it. And it might even be something like the 2x32 Cell chip that got canceled, provided it is compatible with Sony's software.
Heaven only knows what Microsoft is thinking for its future game consoles, which are based on its own "Xenon" three-core variant of the Cell chip, or what Nintendo has planned for its future consoles, which use the "Broadway" single-core Power chip. Software compatibility is key for these consoles - up to a point. Getting consumers to buy new consoles and new games is sometimes more important, which means the console biz could be up for grabs.
But what is perfectly clear is that IBM, which had high hopes for using Cell chips as adjunct processors for commercial systems, is no longer interested in this approach and is taking Cell concepts and adding them to more mainstream Power processors.
That said, it seems very unlikely that the future Power7 chips, due in the first half of next year, will sport SPEs like the Cell did. (IBM certainly hasn't talked about this, and the eight-core chips already have decimal and multiple vector math units per core). But given the more flexible nature of the SPEs compared to relatively static math units, it is not beyond the realm of possibility that Power7+ or Power8 chips have SPEs.
Ditto for future BlueGene massively parallel supercomputers. IBM already packs four 850 MHz PowerPC 450 processors onto a single ceramic processor card, linked by symmetric multiprocessing, so they can share 2 GB of DDR2 memory in the current BlueGene/P supers.
The future "Sequoia" massively parallel super that is going into Lawrence Livermore National Laboratory - with over 1.6 million cores and packing over 20 petaflops of performance when it is delivered in 2011, as we told you when the deal was announced this past February - is not based on Cell or an x64-Cell combo, but what appears to be a packaging of eight PowerPC chips on a single piece of ceramic (not eight cores on a single chip, but eight chips in a package). It is possible that IBM might add SPEs to these cores or math co-processors of some other kind to the package.
Whatever Big Blue is really up to when it talks about hybrid computing with Power chips, it ain't saying - not yet. But the company is telling customers that the current QS22 is the last Cell-based blade it will make. And when you do the math, this means that future 2x32 Cell chip is kaput, fini, no mas, null. Unless Sony, Toshiba, Microsoft, or Nintendo wants to help pay for its development costs. ®