Original URL: http://www.theregister.co.uk/2009/09/22/amd_fiorano_chipset_feeds/

AMD chipsets: the feeds and speeds

And RAID compliments of Dot Hill

By Timothy Prickett Morgan

Posted in Servers, 22nd September 2009 16:03 GMT

X64 chip seller Advanced Micro Devices launched its "Fiorano" family of homegrown server chipsets yesterday, but many of the technical details of the three different chipsets were not available at press time. El Reg has finally got its hands on the specs.

AMD was originally expected to come out with one chipset, which is based on technology the company got through its acquisition of ATI Technologies, which made PC, workstation, and server chipsets as well as graphics cards.

Late last year and earlier this year, the Fiorano platform was described as the SR5690 I/O hub. This supported the 'IOMMU' I/O virtualisation technology, PCI-Express 2.0 peripheral slots, and the SP5100 southbridge, for linking to USB and SATA ports and offering legacy PCI slots. This Fiorano platform was created to support any Rev F socket and includes HyperTransport 3 links. For all practical purposes, the Fiorano chipsets are aimed at quad-core "Shanghai" and six-core "Istanbul" Opterons, which have HT3 links on them (which can deliver 5.2 GT/sec of bandwidth).

These chips support DDR2 main memory, and when the "Magny-Cours" Opteron 6000 (eight and twelve cores) and "Lisbon" Opteron 4000 (four and six cores) are available next year, they will have DDR3 main memory controllers and will reach out to DDR3 main memory through those HT3 links, offering memory performance that is more in balance with the faster interconnect.

AMD yesterday launched three different chipsets, which included two other I/O hubs - the SR5650 and the SR5670 - that are paired with the SP5100 southbridge. All three pairings support PCI-Express 2.0 v1.0 peripheral slots and have SMP support built in as well. They all sport AMD Vi virtualisation technology, including IOMMU v1.2 support, and all three can be used to support a variety of processor sockets. These include the 1,207-pin Rev F socket (for Opterons used in workstations and servers), the 941-pin AM3 socket (for Phenom II processors used in single-socket PCs and workstations), the future C32 socket for Opteron 4000 chips, and the future G34 socket for Opteron 6000 processors.

The main differences between the three pairings have to do with how many PCI-Express engines are on the chip, how many PCI-Express lanes they deliver, and how much juice the I/O hub burns. The SR5650 has eight engines and 22 lanes, and has a maximum thermal design point of 13 watts and an idle power rating of 7.1 watts. This is the I/O hub that will be used in the most energy conscious platforms.

The SR5670 has a max TDP of 17 watts and an idle power of 7.3 watts. It is hotter because it has nine PCI engines and offers 30 lanes. The SR5690 has eleven engines and 42 lanes, and is rated at 18 watts TDP and 7.5 watts idle power consumption. The SR5690 supports hot-plug PCI-Express 2.0 peripherals, while the two smaller I/O hubs do not.

The SR5100 southbridge has support for a dozen USB 2.0 ports and two USB 1.1 ports, and it allows for USB ports to be disabled. The southbridge can also be used to support legacy PCI peripheral slots that adhere to the rev 2.3 spec. It supports SATA disk ports running at 3 Gb/sec, and up to six ports can be put on a mobo using it.

Why not SATA 6Gb/sec ports, you ask? Good question. Faster SATA ports had better be there for next year's "Maranello" platform for the Opteron 6000 and 4000 processors, and it would be useful to have a lot more data ports available, too.

Here's why. The SP5100 also has a virtual RAID adapter based on Dot Hill's RAIDCore VST software, in the BIOS for Fiorano platforms with hooks into the southbridge to support software-based RAID. It would be very interesting - and economically competitive - to have server boards based on Opteron processors with lots of SATA ports that obviate the need for a PCI-Express RAID controller in the first place. With the amount of processing capacity on the servers, running the RAID algorithm on a machine with four to twelve cores per socket is no big deal. For cloud and Web applications, where redundancy is built in at the cluster level, getting rid of the cost of RAID controllers could be very attractive. Ditto for workstations.

One interesting thing relating to the Fiorano and Maranello platforms - according to Longoria, server and workstations senior product manager at AMD - is that the tier one server makers are not planning on using these chipsets right now. Instead, they are focusing on products for the beginning of next year, starting with Maranello platforms using the Magny-Cours Opteron 6000 processors in the first quarter.

That's not the interesting bit. The interesting bit was that Longoria said that in some cases, server makers were noodling around with using two SR5650 I/O hubs instead of one SR5690 hub. You can obviously do that if you want to get more PCI-Express lanes or, as I am saying above, more SATA ports on the motherboard. Thanks to HyperTransport point-to-point interconnects, using two chips instead of one can work.

I can envision a very dense SATA-based disk array that has lots and lots of SATA ports right on the motherboard, akin to Sun's X4500 and X4540 "Thumper" storage servers, using multiple SR5650 along with multiple SP5100s, yet still offering an SMP configuration for the Opteron chips on the server. ®