Boffins design ferroelectric Flash cell for 'super' SSDs
Tech to boost Flash longevity, slash write times
Japanese researchers have developed a NAND Flash cell design they claim will make solid-state drives not only faster but also more reliable, with a longer lifespan.
Led by University of Tokyo Engineering Department Associate Professor Ken Takeuchi and Shigeki Sakai of the Frontier Device Group within Japan's Advanced Industrial Science and Technology institute, the scientists created a ferroelectric Flash memory cell - aka Fe-NAND - with a non-volatile page buffer.
Traditional Flash cells use an electrically isolated Floating Gate (FG) layer, which holds a charge that governs whether the Control Gate above it conducts or resists a current - effectively an on-off switch that can be used to store binary 1 or 0.
Because it is surrounded by an insulating material, the FG can hold its charge indefinitely - to all intents and purposes - even when there's no power feed to the cell. The FG may not be electrically connected to the rest of the cell, but it is connected capacitatively, allowing electrons to be moved back and forth using quantum tunneling.
The Tokyo team's cell replaces the FG with a ferroelectric layer - SrBiTaO - that can be permanently polarised, allowing it to retain a bit of information when no power is running through the cell. Polarising the ferroelectric layer requires a much lower voltage than that which must be applied to the FG, they said.
The Tokyo team's Fe-NAND cell
FG-based Flash cells require voltages upwards of 20V to set the cell's value, whereas the Tokyo team's cell can do it with 6V, they claim.
They also believe the structure has a longer write-life than the traditional one, which typically can undergo 100,000 write cycles before becoming inoperative. The team didn't specify the longevity of their cell, but they did say that further development work could yield a life of 100 million write cycles.
Fe-NAND chips should be cheaper to produce too, the team believes, as the structure can be used at fabrication process scales of 10nm and below, sizes at which the properties of traditional Flash cells break down.
The cell's improved speed characteristics will come from better data writing algorithms that reduce the degree to which chunks of data are fragmented across the array of Flash cells within the memory chip. Information is stored in a Page Buffer and later written out to the Flash array as a whole to prevent fragmentation, which would otherwise add a hefty penalty to random write operations.
This technique is being explored by other researchers, but the Tokyo team added a non-volatile Page Buffer to their cell, to ensure that data isn't lost if the power is cut between the act of filling the buffer and subsequently writing it out to the Flash.
Takeuchi and co. will be detailing their design at the 2009 Symposium on VLSI Circuits which opens in Kyoto today. ®