Intel's future Xeons to share sockets
Westmere mobo tock but no tick
We know what's coming on desktops and notebooks. But what about Intel's 32 nanometer server silicon?
Intel's 32 nanometer process will be used to make a family of desktop, laptop, and server processors known as "Westmere," kickers to the Nehalem chips that will roll out throughout the year. Earlier this week, the company divulged that it was pulling its ramp to 32 nanometer chip making processes into 2009 for desktop and laptop processors, and it gave us a pretty idea of what these chips will look like.
What Intel didn't say is how it will deploy cores or crank up clock speeds on 32 nanometer server chips. Intel has some interesting options, as the Nehalem and Westmere desktop and laptop chips show.
On its desktop lineup, Intel is taking two different paths. With the Nehalem chips, which are implemented in its current 45 nanometer processes, the company is deploying quad-core "Lynnfield" chips, which have two threads per core, and it will offer a similar "Clarksfield" chip for laptops. These chips are similar to the current Core i7 desktop chips, which have been shipping for high-end desktops since last November and will arrive in volume this year across the full PC spectrum.
In the second half of this year, Intel is going to use the 32 nanometer shrink not to increase the core counts in its desktop and laptop chips, but rather to move an integrated graphics controller onto a two-chip package. The future Westmere desktop and laptop chips will have only two cores, and the main memory controller that is integrated on the Nehalem chips is being moved over to the graphics controller that will sit beside the Westmere two-core chip.
That graphics chip and memory controller will be implemented in a 45 nanometer process, which will undoubtedly deliver higher yields and lower costs than if they had been done in 32 nanometer processors as a single chip Westmere package. The processor and graphics chips on the Lynnfield and Clarksfield packages will be connected by a QPI (Quickpath Interconnect) link.
Server processors do not need to have integrated graphics chips on their packages, unless you want to use the GPU as a math co-processor. (Not a dumb idea, provided the programming model is easy). Even if Intel doesn't want to do that, the 32 nanometer shrink for Westmere Xeons could allow the company to do all sorts of things: add more processor cores in the same thermal envelope, crank up clock speeds to boost single-thread performance while holding core counts the same or even decreasing them, or integrate other features (such as network controllers) into the chip package.
In addition to the Westmere roadmap this week, Intel confirmed that the launch of the Nehalem EP processor for two-socket servers was imminent. It's expected before the end of this quarter. The Nehalem EPs (aka Xeon 5000s) will plug into the Tylersburg server platform and use a chipset by the same name, as this roadmap shows:
Back in November, we gave you the feeds and speeds on Nehalem EP motherboards from Super Micro, which makes boards as well as whitebox servers that it and other vendors sell. The Nehalem EP chips, which sport integrated DDR3 memory controllers and which will be the first servers to use QPI, are expected to have somewhere between three and four times the memory bandwidth of existing Xeons and their antiquated front side buses.
Exactly how this will translate into application performance will depend on how sensitive those applications are to memory. The Nehalem EP chips, code-named "Gainestown," are expected to come in two-core and four-core variants, with each core having two threads and with either 4 MB or 8 MB of L3 cache. These chips are basically a version of the Core i7 desktop chip reimplemented with symmetric multiprocessing extensions. Clock speeds are expected to range from 1.9 GHz to 3.2 GHz.
The high-end Nehalem EX processors, code-named "Beckton," will have up to eight cores, will be delivered by the end of the year and will use the "Boxboro" chipset that will also be used in the future "Poulson" Itanium processor. The Boxboro chipset will work with QPI to allow a "glueless" SMP configuration with up to eight processor sockets. Technically, the initial Opterons could do this two, by gluing together four two-way motherboards into a single system image, and it looks like Boxboro will glue together two four-socket machines to get an eight-way. The question with either approach is whether server OEMs will do it. Very few adopted the eight-way Opteron configuration.
The low-end Nehalem EN chips are tweaked versions of the Lynnfield chips used in desktops and made with 45 nanometer processes. They plug into a server platform called "Foxhollow" and use the Intel 5 series chipset used on desktops. If history is any guide, these single-socket server boards will have more I/O slots and possibly more main memory than their desktop counterparts.
Looking ahead to the Westmere generation, the future 32 nanometer chips will plug into the Foxhollow, Tylersburg, and Boxboro platforms. This is obviously something that server manufacturers want very much, since they do not like revving their hardware every year. It looks like Foxhollow gets launched in the second half of 2009, and Boxboro at the end of the year, and Tylersburg should have been here already if this roadmap is to scale.
The Westmere kickers to Nehalem EP chips (which have not been given a code name yet) are due around mid-2010, then, and the Clarkdale chip with its integrated graphics processor gets plunked into single-socket servers in early 2010. Don't expect a Westmere kicker to the high-end Nehalem EX until early 2011, it looks like.
The 32 nanometer shrink from Nehalem to Westmere should allow Intel to get clock speeds up around 4 GHz or so, compared to a little more than 3 GHz with Nehalems and their 45 nanometer processes. Or Intel could boost the core count and keep clocks about the same. The expectation is that Intel will go for speed, not cores. But the company could just as easily put two Westmere chips side-by-side in a single package instead of revving the cores, or leave graphics processors into some Westmere Xeons (as it did for the low-end Clarkdale chip) to use as a co-processor for applications.
It would be interesting to see HPC variants of Westmere chips with the graphics units embedded and then two-chip Westmere packages for regular commercial processing workloads. Intel could put other features inside a package as well - or just make the chip smaller and keep the thermals low, offsetting some of the higher heat that DDR3 main memory kicks out compared to DDR2 memory.
Out beyond that, Intel will launch a new "Sandy Bridge" chip architecture in 2010 or 2011 (it depends on the roadmap you look at) with 32 nanometer processes, and it will eventually shrink this family of chips using 22 nanometer processes in 2011 or 2012. ®