Original URL: http://www.theregister.co.uk/2009/02/05/intel_delays_tukwila/

Chipzilla sits on its Tukwila

Itanium delayed six months

By Timothy Prickett Morgan

Posted in Servers, 5th February 2009 17:36 GMT

Chip maker Intel has quietly copped to another delay with its "Tukwila" quad-core Itanium processors.

The company is revamping the quad-core Tukwila processor design, which will push deliveries of the chip out to the middle of this year. And that means system shipments will be even later. This six-month hold-up is by no means the worst Itanium delay, and it's the smart thing to do.

Tukwila was originally expected in 2006 or maybe early 2007, depending on the leaked roadmap. Then Intel was supposed to have the processors finished and ready to go at the end of 2008, and a handful of OEM partners - including HP, Fujitsu, NEC, and Bull - were expected to begin shipping systems right about now, after a few months of intensive validation procedures.

Somewhere along the line, Intel and its OEM partners decided to ditch DDR2 main memory for Tukwila and switch the chip to buffered DDR3 main memory. This is the same kind that will be used in the forthcoming "Nehalem" line of Xeon servers, also expected to start shipping soon.

The Nehalem servers were originally expected in February and there has been talk that they might ship by the end of March. That date for Nehalem Xeons might not hold - if Intel decides to use the economy as an excuse to delay the arrival of Xeon chips it has already made. Its channel partners may talk it into pushing Nehalems out to mid-year, when the economy might be better.

Anyway, the Tukwila chip has two integrated main memory controllers, and the shift to DDR3 main memory means swapping out the DDR2 memory controllers and plunking down DDR3 replacements. The memory controllers are not integrated into the Itanium cores themselves, which makes this job easier.

The Tukwila memory controllers sit on two sides of a crossbar router embedded into the heart of the chip, linking the cache directories, the caching agents that front end the L3 caches attached to each Tukwila core, and the QuickPath Interconnect ports.

Intel was telling customers they would get about six times the memory bandwidth with Tukwila chips compared to Montvale Itaniums. It is unclear how the shift to DDR3 main memory will affect bandwidth. The Tukwila chip, which has nearly 2bn transistors, will have 30MB of L3 cache on the chips.

Speeds are expected to range from 1.2GHz to 2GHz, and the top-end Tukwila is expected to deliver about twice the performance of the Montvale Itanium 9100 running at 1.66GHz. The fastest parts are expected to have a 170-Watt thermal envelope, which is hot but no worse than big RISC chips with which Itanium competes. They are implemented in a now-old 65 nanometer process, but one that Intel knows how to push to the extremes of yields.

The other big change made on the Tukwila chip was to move it to the same socket type that will be used by the future "Poulson" and "Kittson" Itaniums. The Tukwila chip had its very own socket, which means it cannot be plugged into existing Itanium machines that use the front side bus architecture.

By bringing the Poulson socket forward, Intel's OEMs are going to be able to milk their server designs for the next three generations of Itanium, much as they have been able to do with the last three: single-core Madison, dual-core Montecito, and dual-core Montvale chips (I'm being generous calling Montvale a different generation).

Details on these future Itaniums are thin, but Poulson will have a new "advanced multicore architecture," according to roadmaps, and will be implemented using a 32-nanometer process. Kittson is the ninth Itanium generation, and other than that, Intel has said very little about it.

A year ago, there was some chatter that Poulson might come to market in late 2009 and possibly have six or eight cores. But it would be odd to see Poulson much before 2010 at this point, and it will probably arrive later in the year given that Intel will want to have ramped up the 32-nanometer chip making processes fully before putting Itanium on it. Kittson might appear in 2012 or so.

CSI Intel

For those of you who remember ancient Xeon and Itanium history, the Common System Interface effort that was launched by a battered Intel in early 2004 had two elements. The first was that Xeon and Itanium machines would have a common, HyperTransport-like point-to-point interconnect that was much better than the front side bus and chipsets Intel has used with Xeons and Itaniums to date. The Nehalem Xeons and the Tukwila Itaniums are the first machines to implement this technology, which we know as QuickPath Interconnect, or QPI.

The second element of the CSI effort was to have Xeon and Itanium processors using a common set of chipsets and processor sockets so companies could build systems to support either kind of processor. Given the low volumes of Itanium machines relative to Xeon boxes, this is clearly a good idea to help server makers cut costs.

Itanium Roadmap 2008

Intel's April 2008 Itanium Roadmap

The new Tukwila-Poulson-Kittson chips will not share the same socket as Nehalem boxes, according to Intel. But as the roadmap above shows, Intel has been telling people since April 2008 - when this roadmap was created - that Tukwila and Xeon MP chips would have common chipsets. In this case, it is a chipset codenamed "Boxboro."

According to Intel, HP and other OEMs also had a hand in the decision to delay the quad-core Itanium chip so it could get some technology tweaks. "We made the decision along with the OEMs," says Patrick Ward, an Intel spokesperson who handles the Itanium product. "It was a joint decision and we felt that this would benefit OEMs and end user customers. We did not make these changes alone."

It is hard to tell who rues the Itanium partnership more, Hewlett-Packard or Intel. The chip maker should have never listened to HP and created the EPIC architecture, which helped HP support HP-UX better. It might be technically superior to the x86 and extended x64 architectures, but Itanium was no better off in the marketplace than HP's own PA-RISC chips or Sun's Sparcs or IBM's Powers.

HP has put all of its HP-UX eggs in the Itanium basket, so it has to deal with these delays. At this stage in the Itanium game, it may be HP, not Intel, that gets hurt most by continuing delays in the Itanium roadmap.

Lucky for Intel and HP, Sun Microsystems' 16-core "Rock" UltraSparc-RK chip is running late, being delayed by a year, and who knows whether IBM will get a Power6+ chip out the door. It could be a crank on the current dual-core Power6 or a jump to a quad-core design. Or it could never see the light of day.

With the economy in the dumps and enterprise customers who buy Itanium boxes slamming on the spending brakes - and IBM's eight-core Power7 chips not expected until early 2010 - Intel and HP have a little breathing room. ®