Original URL: http://www.theregister.co.uk/2008/12/16/mlc_cpm_pcm/
Flash cells near shrinkage limit
Volatility threatens non-volatile memory
IEDM You call it flash memory. The engineers at this week's International Electron Device Meeting (IEDM) in San Francisco call it non-volatile memory.
According to Stefan Lai of BeingAMC, there's plenty of money to be made in non-volatile memory, whether it's based on the common flash technology or on emerging replacements. A cool $20bn was spent on non-volatile memory in 2008, with $25bn expected next year, financial Armageddon or no financial Armageddon.
There's one big problem, though: Current non-volatile technology is running up against a "natural limit," Lai said during an IEDM talk entitled "Non-Volatile Memory Technologies: the Quest for Ever Lower Cost". And, no, it's not that it is getting harder and harder to make smaller and smaller non-volatile memory chips. Lai says that the lithographic technologies needed to shrink the chip elements are good down to at least 22nm, maybe even further.
No, the problem is much simpler - and more intractable - than that. Memory-cell sizes are getting so small that they soon won't have room for enough electrons to keep the non-volatile memory, well, non-volatile.
"When I started," the veteran memory designer said, "I had a hundred thousand electrons [in a cell], so if I lost one per day, I had no problem." Today, there's a problem. As Lai puts it, in upcoming memory cells, "you're counting tens of electrons."
It doesn't take a statistical genius to see that losing one electron out of tens will be a far bigger deal than losing one electron out of 100,000. The problem will be - do the math - 10,000 times bigger.
Something needs to be done - and it needs to be done cheaply and reliably. Chip elements are now around 1000 times smaller than they were when non-volatile memory started to make its move in the mid-1980s. Prices have shrunk as well - they're now about one two-thousandth of what they were in 1986, said Lai.
According to Lai, the $1-per-gigabyte price threshold is the "tipping point" for flash acceptance - and he made a point of saying "and as those of you in business understand, price and cost are not the same thing." We're at that $1/GBybte point today - and there's no going back.
So how will the non-volatile industry keep things cheap while continuing to expand capacity? Before you read on, be forewarned: The acronyms will come thick and fast.
Lai says that the answer is multi-layer cells (MLC) using cross-point memory (CPM) architectures - cross-point memory being, in essence, an architecture in which a memory cell is formed where a metal memory bus and a silicon memory bus meet, or "cross". A cross-point architecture can be quite dense in cells per volume of chip.
Lai says that there are a few competing technologies for the cell in his envisioned non-volatile savior, but he's a fan of Phase-Change Memory (PCM). According to Lai, compared to its two main competitors, Resistive RAM (RRAM) and Programmable Metallization Cell (PMC), PCM is "the most developed so far." It also has a "RAM-like" read/write life of 10^10 cycles, its switching time is good ("and improving"), and its switching current is high ("and improving").
RRAM, according to Lai, is hampered by a low read/write-cycle lifetime and the fact that it hasn't yet been manufactured in high densities. PMC has a good life expectancy of 10^6 cycles, and a fast switching rate. One reason that Lai doesn't lean towards PMC, however, is that its low voltage requirements make it - according to Lai - more susceptible to signal variations and noise.
Lai ended his talk with his vision of PCM replacing most DRAM in computer systems - a computer's speedy DDRx DRAM allocation would be small compared to a large complement of PCM, and it would act as a quick-access buffer for the PCM. To achieve this, Lai suggested that memory-module manufacturers take a page from hard-disk drive (HDD) manufacturers, and build error-detection and correction more robustly into their systems, much as solid-state drive (SSD) manufacturers have begun to do.
And so, according to LAI - uh, Lai - expect to see MLC PCM CPM in DDRx DRAM with HDD and SSD ECC.