Original URL: http://www.theregister.co.uk/2008/11/28/sandisk_3xmlc_nand_technology/

SanDisk flash holds secret flash sauce till after Christmas

Makes 3-bit MLC SSDs feasible

By Chris Mellor

Posted in Storage, 28th November 2008 19:02 GMT

SanDisk is soon to announce new technology needed for its solid state drives to take on hard disk drive storage.

SSDs are appearing in netbooks and notebooks and in enterprise storage arrays where they provide accelerated I/O, either as a separate tier of flash storage or as a flash cache accelerating the array controller's operations. But the appeal of flash SSD technology is limited because today's NAND chips don't have enough capacity, making them expensive. Writes take too long, being slower than reads, particularly random writes, and the write cycle endurance is too short with the flash wearing out after a set number of write cycles.

SanDisk thinks it can solve all three problems. By adding bits to a NAND cell it can increase capacity with 2-bit multi-level cell (2x MLC) technology here and higher-capacity 3- and 4-bit MLC coming. It has also come up with its Extreme Flash File System (ExtremeFFS) to accelerate random write speed by up to 100 times and so be much closer to sequential write speed.

But it is not enough. SanDisk's Senior Director of Marketing, Don Barnetson, revealed this at a Tokyo press conference on 27th November, saying: "We need one more step of improvement besides ExtremeFFS." He didn't say what that was but he did say: "Please wait a little while for our announcement ... We are preparing a technology to solve these issues." That sounds pretty confident and senior directors of marketing don't tease us so unless something is real and pretty close.

Why is it needed? An exacerbating factor is that NAND chip size is shrinking at the same time as cell bit count is rising; a hard trick to pull off. SanDisk 2-bit MLC flash is being made now with a 43nm process while 3-bit MLC chips have been made with a 56nm one. SanDisk is introducing its 3-bit and 4-bit MLC 43nm chip technology now, at the end of 2008, with an even smaller sub-40nm process coming into play towards the end of 2009. The 3x MLC 34nm chips have 32 Gbit capacities with the 4x ones having 64Gbit capacities.

Increase the cell bit count and capacity per chip shoots up. Shrink the die size and capacity per wafer goes up. Costs goes down in both cases. That's what SanDisk wants, what it needs, but customers aren't going to buy the SSDs unless performance is overall way better than hard drives.

The word is that 3x MLC NAND has lower rewrite performance than 2x MLC. Presumably 4x would be worse again. That's what the new technology is needed for, to make 3- and 4-bit MLC flash acceptable in the performance stakes.

We hear that SanDisk will announce its new secret flash sauce at CES in Las Vegas, January 7-8, next year. The gambling casino capital of America seems exactly the right place to make an announcement about big chips and stake your place at the HDD replacement table. ®