Original URL: https://www.theregister.co.uk/2007/01/16/dense_chip/
HP gets denser, faster...
With nanowire chip advance
HP claims to have made a chip design breakthrough that could result in integrated circuits up to eight times denser than those currently in production.
The new technology would also use less energy per transaction than today's chips, if HP's computer models are correct.
The research has been published in the 24 January issue of Nanotechnology, titled "Nano/CMOS Architectures Using Field-Programmable Nanowire Interconnect".
The breakthrough specifically relates to field programmable gate arrays (FPGAs). For those not dealing with such things on a daily basis, HP explains that these are "integrated circuits with programmable logic components and interconnects that can be adapted by end-users for specific applications". CMOS, of course, stands for complementary metal-oxide semiconductor, the stuff of all chippage.
"As conventional chip electronics continue to shrink, Moore's Law is on a collision course with the laws of physics," said Stan Williams, co-author of the paper and director of quantum science research at HP Labs.
"Excessive heating and defective device operation arise at the nanoscale. What we've been able to do is combine conventional CMOS technology with nanoscale switching devices in a hybrid circuit to increase effective transistor density, reduce power dissipation, and dramatically improve tolerance to defective devices."
The new approach involves building a nanowire crossbar above the transistor layer. The CMOS then handles all the logic operations, while the nanowire deals with the signal routing. This frees up an enormous amount of processing power, since traditionally, between 80 and 90 per cent of traditional CMOS is used for signal routing.
Although the research currently exists only in a simulation, HP has started work on a real world version, and the researchers reckon it could have a working laboratory prototype within a year. Nothing if not ambitious, they estimate that their model, which uses 15-nanometer-wide crossbar wires over 45-nm half-pitch CMOS, could be technically viable by 2010. ®