Original URL: https://www.theregister.co.uk/2006/05/16/amd_next_gen/
AMD unveils 'next gen' CPU plans
It's more of the same, but faster - official
Processor Forum AMD confirmed details of its "Next Generation Processor Technology" today, but it's really business as usual for the company. As AMD heads to four-core country, the company will continue to improve the bandwidth of its processor package, tweak memory and rely on help from partners to compete with an upcoming line of revamped chips from Intel.
Close AMD watchers will not be taken aback by any of the revelations made by senior fellow Chuck Moore today at the Processor Forum in San Jose. More than anything Moore just put an official stamp on what has been known for months.
The company still plans to deliver a four-core chip in 2007 and expects the product to compete well on overall performance and performance pet watt metrics. AMD pitches the no surprises approach as an advantage over Intel, which in the second half of this year will release a completely new processor architecture across its server, desktop and mobile lines. Even beyond that, Intel is expected to release more architectural changes in the coming years as it tries to improve memory performance.
The chips built with this design will have a few key changes over current products.
First off, AMD is touting a speedier version of HyperTransport that can handle 5.2 gigatransfers per second. The HyperTransport technology has proved key to AMD's performance edge over Intel. AMD expects more server makers to start shipping boxes with HTX slots that allow for add-on cards to slot into the HyperTransport framework, although companies such as Sun Microsystems continue to portray HTX as a niche play for the moment.
The second major change will be the presence of shared L3 caches in AMD's upcoming chips. AMD will continue to have "private L2 caches" but will add the on-chip L3 cache to improve overall performance.
"We believe this strikes the right balance," Moore said, during a speech. "This is a really interesting way to handle the memory hierarchy and it's in stark contrast to the brute force method (used by Intel)."
Intel has relied more and more on enormous caches to improve its chips, although the company seems to be moving away from that practice in future products.
AMD has also added better power management tools, so that a system can independently power the north bridge and CPU. In addition, future chips will have twice the floating point performance, support for 1GB memory pages, DDR2 and DDR3 (when it arrives) memory support, FB-DIMM memory support and improved RAS features such as memory mirroring and memory diagnostics.
Overall, AMD is concentrating on keeping single thread software performance high, while paving the way for more multithreaded applications. Moore urged the chip industry to provide "hooks" that can make designing multithreaded applications easier.
Today, AMD claims to enjoy up to a 95 per cent power consumption advantage over Intel. Even when Intel releases its new products, Moore claimed that AMD would still have a 43 per cent power consumption advantage, although apples to apples comparisons are close to impossible at the moment due to a lack of Intel product.
AMD expects more co-processors to start popping up for its chips in the coming years to help out with tasks such as Java, TCP/IP and SSL processing. The company's open specifications tend to make it easier for third parties to create products around AMD's gear than is the case for Intel, although Intel does enjoy a large partner network thanks to its massive market share.
Moore continued to knock Intel's dual-core and future four-core products as not being actual multicore gear for the most part. Intel has tended to create multi-core products by simply packaging numerous cores next to each other rather than building them into a single die.
AMD was able to secure a performance lead over Intel by arriving first to the 64-bit scene and then following that with dual-core products. The company, however, now seems to have run out rabbits to pull out of the hat. It's all about execution now, according to the little chipmaker that could. ®