AMD quad-core Opterons to gain L3 cache in 2008?
Gaining FB-DIMM support too, report suggests
Roadmap AMD is scheduled to launch quad-core Opteron processors capable of supporting Fully Buffered DIMM memory and sporting an extra level of cache shared by each of the fourt cores, it has been claimed in a roadmap-revealing report online.
According to Japanese-language site PCWatch, AMD's second-generation quad-core Opterons will ship in Q2 2008, less than a year after the first quad-core server chips arrive early in H2 2007.
The first quadies, which will succeed the current Opteron 2xx and 8xx CPUs, are codenamed 'Deerhound', and they're essentially a doubled-up version of 'Santa Rosa', the next-generation dual-core Opterons due in Q3 this year. All these processors will support registered DDR 2 SDRAM memory and support AMD's virtualisation technology, currently codenamed 'Pacifica'.
'Zamora' is what AMD is allegedly calling the second-generation 2xx and 8xx quadies, which are said to support FB-DIMM memory and HyperTransport 3. A four-core Opteron 1xx part, codenamed 'Cadiz', is said to be scheduled to ship in the same timeframe.
Surprisingly, Athlon 64 and Athlon 64 FX quad-core may appear before the server chips. 'Greyhound', the follow-on to the 65nm dual-core desktop chip 'Brisbane', looks set to launch early to mid-H1 2008, just ahead of the Opterons. Like Cadiz, it's said to support DDR 2 and DDR 3, along with HyperTransport 3.
Zamora, Cadiz and Greyhound are all said to based on a new incarnation of the K8 core, first launched in Q3 2003 and revised numerous times since. They'll also be 65nm parts, though AMD's arch-rival, Intel, has said it will be preparing 45nm parts by then. AMD's slower migration to 65nm doesn't appear to have done it any harm, though it's now up against a revitalised rival that's adopting a radical, two-year architecture revision programme. ®