Original URL: http://www.theregister.co.uk/2005/08/26/cell_cpu_interfaces_published/

Cell chip mysteries revealed

It's all about helping the Fire Brigade...

By Andrew Orlowski

Posted in System Builder, 26th August 2005 07:25 GMT

The much-anticipated Cell processor just got a little less mysterious, as IBM unloaded a heap of documentation for the public to peruse.

Free registration is required to download the 331-page Cell Broadband Engine Architecture overview, the ABI, and guides for Assembly language and C/C++ programmers. But the Cell's chief architect, Peter Hofsee, has written a lucid two-page guide to the chip entitled "Cell Broadband Engine Architecture from 20,000 feet".

The Cell is a joint venture between IBM, Sony and Toshiba, and will appear in the PlayStation 3, although IBM wants to use it for servers and has even licensed it to medical equipment manufacturer. It's a single chip PowerPC which looks like a 9-way SMP to the programmer. Cell contains two kinds of processor the PPE (Power Processor Element) and the SPE (Synergistic Processor Element), or Cell. The PPE can run existing PPC software (such as Mac OS X), while computationally intensive work is handed off to the SPE.

Hofsee describes the three level organization as "a radical break" with conventional architecture "because it explicitly parallelizes computation and the transfers of data and instructions".

This was necessary, he says, because memory latency has increased drastically in the past twenty years. We're waiting for slow memory rather than on slow CPUs, and if data isn't in the memory cache the CPU misses several hundred clock cycles attempting to catch up. "Even with deep and costly speculation, conventional processors manage to get at best a handful of independent memory accesses in flight. The result can be compared to a bucket brigade in which a hundred people are required to cover the distance to the water needed to put the fire out, but only a few buckets are available."

The Cell attempts to solve this problem using direct memory access transfers to the SPEs, or Cells. Each SPE can establish many of these. By contrast, the explicit DMA model allows each SPE to have many concurrent memory accesses in flight without the need for speculation. And it's this memory design that the Cell team believes gives the chip twice the performance of any other processor.

You can read Hofsee's overview here. ®