IBM, Sony to detail 'Cell' PS3 CPU February 2005
Massively parallel, 64-bit POWER-based processor to debut at ISSCC
IBM, Sony and Toshiba - the three companies behind the 'Cell' microprocessor - will formally detail the chip's workings at the International Solid State Circuits Conference (ISSCC) on 6 February 2005, the trio said today.
IBM and Sony also said they were now ready to announce the promised Cell-based workstation, which should enable software developers to begin coding for the PlayStation 3, itself set to be based on the new chip.
The partners describe Cell as a 64-bit POWER-based "multi-core system" for computers and next-generation digital home appliances. Crucially, each core can run a single operating system, or run their own OS independently of the others. OS options include real-time support.
With the confirmation that Cell is indeed derived from IBM's POWER architecture, and given they way the chip's designers discuss it more in terms of a general-purpose CPU than the more console-oriented Emotion Engine of the PS2, it's clearly going to raise the possibility that the part may be of interest to Apple.
And since IBM is also working on the CPU for Xbox 2/Xbox Next, there's the chance of a certain degree of software compatibility there too, though clearly the use of different high-level APIs will limit games and application portability.
The chip's makers note that Cell is not only a multi-core architecture - like the anticipated 'Antares' PowerPC 970MP - but multi-threaded too, though it's not yet clear whether support for multiple threads takes places within each core level, HyperThreading-style, or Sony and co. are simply talking about spreading threads across cores. IBM's POWER 5 architecture supports simultaneous multi-threading, so it seems likely Cell will too.
IBM and Sony also talk about big memory and I/O bandwidth - no great surprise there, given it's a 64-bit processor and what IBM has demonstrated with existing POWER and PowerPC processors. More interesting is the integration of a security sub-system. The companies don't go into any detail, but it sounds not unlike VIA's PadLock technology with its hardware random number generator. Mention is made of "high-level media processing", which could be a reference to AltiVec, the PowerPC SIMD engine.
There's also the suggestion that Cell will use a SpeedStep-style power conservation technology, allowing the chip to reduced its clock frequency. IBM's 90nm PowerPC 970 already has something along these lines.
Contrary to past speculation that Cell would ship at 65nm, its makers today said it will debut as a 90nm part using IBM's SOI technology.
As for the Cell-based workstation, it's clearly only at the prototype stage, IBM and Sony having come up with an "experimental model".
Still, it packs 2 teraflops into a standard (presumably) rackmount box, apparently, with what sounds like multiple, multi-core chips operating as a kind of cluster-in-a-box configuration. ®
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