Intel plots 4MB L2, 64-bit desktop CPU
Conroe to bring Pentium M family to the desktop
Intel is preparing a multi-core, desktop incarnation of its Pentium M processor with a whopping 4MB of on-die L2 cache and 64-bit x86 extensions.
So claims usually accurate Japanese website PC Watch.
The chip, codename 'Conroe' (a name as yet unconfirmed, the report says), is being developed by the Israeli team behind the first Pentium M, 'Banias', and its 90nm successor, 'Dothan'. The latter is due to ship next quarter.
Banias was a ground-up redesign focusing on power preservation and performance, rather than simply producing a mobile version of the Pentium 4 architecture. Naturally enough, the team are working on the chip's descendants, including 'Merom', which will again sport an entirely new architecture. Like Conroe, it will feature 4MB of cache, a feat made possible by the use of a 65nm fabrication process.
Merom is also expected to include all the technologies Intel has been touting of late, including HyperThreading, the Vanderpool virtualisation system - allowing the chip to run multiple OSes simultaneously - LaGrande security features and, of course, Intel's 64-bit Extended Memory system.
Conroe is believed to be essentially the same part but with desktop roles in mind. In practice, that means a greater willingness to trade power consumption for performance, so you're looking at Conroe consuming 90W to Merom's 45W, PC Watch suggests. That's not only a big improvement on the current generation of 90nm Pentium 4, 'Prescott', but also Prescott's successor, 'Tejas', which is expected to consume around 125W.
Merom will not follow directly on from Dothan - 'Jonah', essentially two Dothan cores on a single die, connected to 2MB of unified cache, is expected to ship first, again fabbed at 65nm. Merom and Conroe are roadmapped to appear in 2006, Jonah sometime next year, probably in the second half and maybe much later, depending on whether Intel suffers the same problems it experienced with its transition to 90nm when it makes the move to 65nm. Delays to Jonah would undoubtedly push back Merom from H1 2006 to H2.
Jonah is likely to be accompanied by a third version of the Centrino platform, dubbed 'Napa'. The chipset itself is codenamed 'Crestine', and is expected to offer a higher frontside bus that 533MHz, 667MHz DDR 2 SDRAM support and feature a next-gen. ICH7-M South Bridge. 'Alviso', the next generation of Pentium M chipset, will take the FSB from 400MHz to 533MHz, Intel has said.
Before Conroe, Intel will ship Tejas sometime next year, followed by 'Cedarmill', a dual-core, 65nm version of Tejas. ®