Mac Rumour Roundup Motorola is pushing ahead with the design of the PowerPC 7500 - aka G5 - company sources have claimed, according to a report over at MacOS Rumors.

We're sure they are, but we're not so sure the report's claims are entirely accurate except in a very broad sense. The report's information is a little too close to the details displayed on Motorola's last publicly released roadmap, dating back to September 1999.

According to the report, the G5 will boast speeds of 2GHz and up, "full-performance backward-compatibility", 512KB of on-die L2 cache a new memory architecture and a modular design allowing the company to offer multi-core chips. It will be fabbed at 0.1 micron using silicon-on-insulator construction.

The 2GHz speed comes straight from the (undated, ie. 200x) roadmap, and marks a very broad goal, especially since we're not even at 1GHz yet. MacOS Rumors' report says the G5 will have a deeper instruction pipeline, but since you have to have that to support such a high clock speed, that's no great surprise.

The PPC 7450 has 256KB of on-die L2, so extending that to 512KB is so obvious a move, you can take it as read.

The fabrication and SOI references also come straight from the roadmap. SOI is certainly very likely in next-generation PPCs, as we reported yesterday in our coverage of Motorola's new HiP7 0.13 micron process technology. It's worth noting that the roadmap has the PPC 7450 (aka G4 Plus) fabbed at 0.15 micron, but in fact it's fabbed at 0.18 micron. Given that Motorola is only now making its initial production forays into 0.13 micron, we reckon 0.1 micron is a long way off. The point is, the roadmap is all pie-in-the-sky stuff, so it's important not to take it at face value.

The roadmap also notes the G5's "new bus architecture", which MacOS Rumors has taken to mean MaxBus, the 128-bit bus originally planned to debut with the G4 Plus. That chip was also expected to contain Motorola's multi-core design approach but never did, so the report reckons the G5 may get it instead.

We're not saying all this has been made up, simply that it's too generic to give a detailed picture of what Motorola's engineers are up to (though we'd welcome them to put us right on the matter).

So is there anything in the report that's not roadmap and 'next logical step'-derived speculation? Two points interested us: that the chip is based on IBM and Motorola's Book E spec., and that it will launch at 1.2GHz. Book E emerged back in 1999 when the two companies shook hands and attempted to convince the world that they really hadn't fallen out over the future of the PowerPC platform.

Book E was invented to indicate they were in harmony over the platform's development for the embedded market. How that applies to desktop computing applications, we're not sure. Neither company has had anything to say about Book E since 1999, so we suspect that whatever new developments it was likely to have included - copper, SOI, 0.13 micron - have made their way into the platform already or will be coming soon.

As for the 1.2GHz launch speed, that's possible, but probably too early to say.

Certainly the next PowerPC chip Motorola is known to be working on, codenamed Apollo, is aimed at taking the G4 family above 1GHz. Given Intel is launching a 1.7GHz Pentium 4 in two weeks' time and will have 2.2GHz P4s out at end of the year, Motorola will have to move quickly on this one.

Whether Apollo is the G5 or a revised G4 Plus, isn't yet known. It certainly sounds more like the latter than the former. Unveiled last October, Apollo will use SOI and be based on 0.18 micron process, Motorola said, this and a deeper pipeline will permit the higher clock speeds. It will also feature a wider, 256-bit path between on-chip caches, on-die L2 cache of 256KB and up to 2MB of external L3 cache. ®

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