What does 130nm mean to the man on the Clapham omnibus?
With Intel and AMD/Motorola's joint efforts on moving to 130nm processes about to go head to head (Story: New Intel, Motorola/AMD chips face off), it's perhaps an opportune moment to look at how semiconductor technology has progressed over the last decade or so.
Intel's first microprocessor, the 108KHz 4004, was built using 1971's state of the art ten micron process. By 1989, the P648 process was used to build the first 486. This was a one micron process producing chips with a gate length of a micron and an SRAM cell size of 220 square microns. With only two layers of interconnect, the end product needed five volts to drive it.
When the original Pentium arrived in 1993, things had moved on again. The 0.80 micron P650 process meant that the three million transistor 60MHz part was little bigger than the 2,300 transistors of the 4004.
The first P6 architecture processor, The Pentium Pro, arrived towards the end of 1995, built on the P854 0.35 micron process that was also used for the first Pentium II launched two years later. The SRAM cell size was now down to a tenth the size it had been six years earlier.
In 1997, Pentium II went through a die shrink to 0.25 micron with the arrival of the P856 process. The SRAM cell shrank to half its previous size at just over 10 square microns. Last year saw the first 0.18 Pentium III using the P858 process with a gate length of 130nm - the same process used today for the Willamette Pentium 4.
Next year will see the 130nm P860 process used to build the Tualatin PIII die-shrink and the Northwood Pentium 4. SRAM cell size using P860 is a hundredth the size of that in a 486, making the provision of large on-die L2 caches simpler. This process also sees Intel moving to copper interconnects - some 40 per cent faster than aluminium - for the first time and reducing the supply voltage to 1.3 volts.
Not only does everything run cooler, but the technology will be capable of producing microprocessors with over 100 million transistors operating at multi-gigahertz speeds. The reduction in gate length to 70nm is expected to improve performance by 50 - 60 per cent over today's 0.18 micron parts.
130nm technology is being developed in Fab 20 in Oregon, with production starting in the first half of next year. Eight other fabs will come online by the end of 2002, producing 200 and 300mm wafers. ®