Silicon nanowires: The Next Big Thing™ in chip design

CPTF 2012 The next step in transistor architecture will likely be silicon nanowires – extremely thin silicon wires that will form the transistor's chanel, surrounded on all sides by a wrap-around silicon oxide, high-K metal gate.

"It's the ultimate fully-depleted device," the director of IBM's Semiconductor Research & Development Center, Gary Patton, said during his keynote address at Wednesday's Common Platform Technology Forum 2012 in Santa Clara, California. "You don't have a gate on just two sides, or three sides – it's fully encapsulating the silicon nanowire device."

Good ol' garden-variety planar – flat – transistors have powered chips for many process generations, and are only now being replaced by three-dimensional FinFET transistors – what Intel calls "Tri-Gate". A good chunk of CPTF 2012 was spent discussing the FinFET plans of the Common Platform's main members – IBM, Samsung, and GlobalFoundries – but next-generation silicon nanowire technology got its share of the spotlight, as well.

Mukesh Khare, IBM's director of semiconductor technology research, introduced silicon nanowire transistors at one of CPTF's sessions by first reviewing the progress that has been made beginning with electron-freeing strained silicon, through the power-leakage protection of high-K metal gate transistors, and on to the fully-depleted (no pesky loose electrons) FinFET/Tri-Gate. "Once we know something and how to get benefit out of it, we keep using it," he said.

These advances have been additive: high-K metal gate transistors are strained, and FinFET transistors have both strained silicon and high-K hetal gates. "It's building on the legacy of the innovation that has been put into the technology roadmap in the past," Khare said.

"And where does it go beyond FinFET?" he asked rhetorically, then answered himself. "Nanowires, which in our view is the ultimate silicon device."

"You go to three dimensions," he said, refering to FinFET, "you're conducting on three planes. You go to nanowire and you're a cylinder. And in a cylinder your gate is all around your device – and it can't get better than that."

Khare said that there's "very good R&D going on" in research labs that's attemting to leverage all the advances in transistor technologies of FinFET and move them into the silicon nanowire future. "We have a huge program going on about nanowires," he said, "studying how you can extend a 3D FinFET process integration and process technology into an ultimate nanowire technology."

Not that silicon nanowires will be introduced in commercial-grade chips anytime soon. There's a lot of tweaking, optimizing, and perfecting – and, of course, scaling – that remains to be accomplished with FinFET-based chips. FinFET "is not going to be a one-generation solution," Khare said, "it's going to be a many-generation solution."

He spoke of work done in 2010 in which his research team was able to use some of the FinFET technology to construct a fully functioning 25-stage ring-oscilator CMOS circuit. "And these nanowires were made down to a size of three-nanometer diameter," he said. Patton mentioned the same device in his keynote, calling it "a big step forward in terms of getting silicon nanowires ready for the advanced R&D phase."

Khare told the assembled chip designers that "Obviously there's a lot of innovation, a lot of work needed to get the current out of the three-nanometer diameter cylinder, but that's our job, and that's what we're all working on making happen." ®

Bootnote

Samsung's Jong Shik Yoon, who currently leads that company's logic development team focusing on 20nm and 14nm, spoke of FinFET scaling down to eight nanometers, and possibly some sort of FinFET-nanowire hybrid scaling down to five nanometers.

"I don't know what's going to happen to get below five nanometers," he said. "But I don't think that most people in this room need to be bothered. I will see, at home with my wife, how our young generation moves forward in the future. That's what I'm going to do."