NAND flash bottleneck being blown away

A looming NAND flash memory bottleneck will be pre-empted by a tenfold increase in data rate due to a new industry standard being promoted by Samsung and Toshiba.

NAND chips in use today generally use a 40Mbit/s single data rate (SDR) interface. There is a toggle double data rate (DDR) 1.0 specification which provides 133Mbit/s. This applies a DDR interface to the SDR NAND architecture. Samsung and Toshiba want to produce a 400MBit/s toggle DDR 2.0 specification which will be three times faster than DDR 1.0. They have committed to do so.

Dong-Soo Jun, memory marketing EVP at Samsung, said that NAND needs to get faster: "The rapid adoption of fourth-generation smartphones, tablet PCs and solid state drives is expected to drive demand for a broader range of high-performance NAND solutions."

Masaki Momodomi, technical executive for memory product at Toshiba, amplified this: "Toggle DDR provides a faster interface than conventional NAND using an asynchronous design, delivering the benefits of high-speed data transfer to a wider market, such as for solid state drive applications including enterprise storage, mobile phones, multimedia terminals and consumer products."

Last month, each company started participating in standardisation efforts for the new technology through the JEDEC Solid State Technology Association.

Toshiba and Samsung say toggle DDR 2.0 NAND memory is expected to be of immediate benefit to mobile and consumer electronics applications, where there is consumer demand for an extra stretch in performance. Its adoption in enterprise storage will require support from Intel and Micron though, whose commitment will also be necessary for toggle DDR 2.0 to become a real industry standard. ®