IBM 'readying dual-core G5'

IBM is preparing a dual-core version of its 90nm PowerPC 970FX processor - aka the G5. Codenamed Antares, the chip will be delivered - likely in sample form - to Apple later this summer.

So claim "well-placed" but unnamed sources cited by Think Secret. In fact, the content of the story comes from a series of posts on the website's forum, and it isn't clear if Think Secret knows the identity of the forum contributor - or is just assuming the source is well-placed.

Either way, the chip, to be formally called the PowerPC 970MP, is said to contain two 970 cores each with its own AltiVec/Velocity Engine SIMD unit and 1MB of L2, up from the 970FX's 512KB, but still without L3 cache support.

It will be fabbed using silicon-on-insulator (SOI) materials, but that's no great surprise given IBM's well-established support for the technique. The die size is 13.23 x 11.63mm, and it is not pin-compatible with existing 970 and 970FX chips.

The 970MP will feature an updated version of the 970FX's PowerTune power management system, which, readers may recall, was designed to synchronise across processors, which suits it will to dual-core CPUs.

The chip is said to clock initially at 3GHz with a 1GHz frontside bus, and Apple has committed itself to using the part, the forum poster claims. The Mac maker will receive prototypes (samples) in August. The part is likely to going into production next January, the poster says, which would put its implementation probably a year from now - WWDC 2005 launch?

The poster doesn't appear to address the process node used for the 970MP. IBM has had problems with its 90nm process, but the 65nm isn't going to be any easier, so 90nm seems more likely, at least for initial versions of the chip. IBM has claimed it will be the first chip maker to offer 65nm processors, some time next year.

Motorola, meanwhile, is working on a dual-core version of its PowerPC G4, due to appear sometime this year. ®

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