Asynchronous processing, multiple cores in SPARC future

After revealing on Wednesday that work on UltraSPARC VI(6) and VII(7) was underway, David Yen, the guy in charge of the microprocessor (and networking and security) work at Sun Microsystems and his team couldn't shut up about their plans yesterday.

When you're used to deploying Kreminological forensics to glean the forward thinking of system companies, this torrent of new information is a welcome surprise.
It came thick and fast yesterday. (Until then, the gwana-gwana ratio been climbing to levels considered dangerous by the EPA).

The SPARC highlights: USVII will deploy asynchronous techniques; USIV will be dual core - but not as we know it, Jim; and oh! blimey, the Valley rumor mill turned out to be correct: Afara is creating multi-chip SPARCs.

In this blizzard of roman numerals, SPARC branding might change. Sun is "seriously thinking" of new branding, the folks said, because all those IIIs and Vs when combined with the 'i' suffixes get confusing. Damn right they do: after Pentium II and III Intel abandoned roman numerals for Pentium 4.

Core curriculum

What's new? UltraSPARCIV will be a multicore chip, that much we already knew, but "not like POWER4," said Yen. "They pioneered two-cored design, but we'd independently started on multicore execution. POWER4 is very good and we agree with that philosophy."

USIV will differ, said Yen, because the cores "under software control can work together as one core. They'll be intimately connected to each other."

"We'd like to postpone the binding between the implementation of the hardware and the application they run," he said according to our slightly garbled notes, but he was clear enough: when applications need the two cores to act as one, the processor obliges. "Many customers use one big machine to run multiple jobs and some require high throughput and some don't - the workloads for data centre and for web services are very different."

"A lot of web services are very lightweight jobs but the volume is amazing: there are thousands of connection requests and file service requests."

"A request needs to be authenticated and not much beyond that; so you don't need to use very powerful processors, because the way to use transistors that way is far less efficient than devoting them into smaller chunks, each one a moderate processor, but more than one or two of them."

Why bother with new processors at all then? Why not have stacks of cheaper, older processors in a big shared memory system?

"A blade is one way to do it. One system with lots of processors in the box. Can you go one step further? I can have fewer CPUs with more cores in them - it's all a matter of degree."

Son of Jalapeno - or UltraSPARCIVi is already underway, he added.

Stop the clock

Yen had hinted that UltraSPARC VII had the benefit of recent changes in the computing landscape: what, exactly?

Jalapeno has introduced asynchronous techniques and we could expect to see this influence the USVII design in a big way.

Completely clockless computing, then?

Not quite.

"Sun has been doing research on asynchronous computing (led by Ivan Sutherland [link]) for more than ten years; after so many years they have learned a lot."

"Asynchronous processors are much more difficult to design; most tools now are for synchronous chips. Asynchronous computing has an advantage - you don't have to wait for the slowest stage; but there are drawbacks. CMOS power consumption is directly related to switching; so if they all switch at the same time, then you get a peak."

The biggest problem for microprocessor designers was clock skew, or delay, and this would require a change in how microprocessor design had traditionally been taught.

"Theoretically there's once clock in a CPU now, but timing arrives at different moments," he said. "You have to distribute that clock to the whole die. There's a delay that the designer has to accommodate. That eats into the total cycle time available to do calculations."

"This is going to change a lot of the design philosophy that's taught in school - you should worry about gates. Cray used to issue papers saying you must have no more than 6 or 8 gates - but now you can have a long wire with no gates that causes more delay."

There's a nice summary of Sutherland's work in an article entitled Scrap system clock, Sun exec tells Async in the EE Times.

Yen also hinted that UltraSPARCs would integrate "networking interfaces and cryptography onto the same processor". Sun has merged networking and security with the processor group, and we could interpret that as a declaration of intent.

That didn't leave us much time for Yen to bash Intel. "When the 90 nanometer version of Itanium happens, UltraSPARC V will be waiting; we're confident and exploring a bigger space than what Intel publicity seems to be focusing on".

Was Afara working on multichip SPARCs, as rumored?

"Something in that direction" he said, circumspectly. ®

Related Stories

Sun discloses UltraSPARC VI and VII, shows IV silicon
Sun chip guru brewing multichip SPARC